Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Many mixes to match litho apps

04/29/2016  The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

The advanced packaging industry has reached its zenith

04/14/2016  To overcome the current market and technology constraints taking place today within the semiconductor industry, new advanced packaging technologies have been developed by industrial companies.

Worldwide semiconductor wafer-level manufacturing equipment market declined 1% in 2015

04/06/2016  Worldwide semiconductor wafer-level manufacturing equipment revenue totaled $33.6 billion in 2015, a 1 percent decline from 2014, according to final results by Gartner, Inc.

Texas Instruments names Devan Iyer Vice President

03/29/2016  Texas Instruments Incorporated (TI) announced that Devan Iyer has been elected vice president of the company.

2015 European SEMI Award honors Paul Lindner

03/08/2016  Paul Lindner, executive technology director at EV Group, is the recipient of the 2015 European SEMI Award.

BiTS: The ever-shrinking package underscores emerging challenges and solutions

02/25/2016  What’s the single area that is being most disrupted by emergent technologies like the Internet of Things (or the Internet of Vehicles) and Silicon Photonics? We think it’s packaging.

Semiconductor capital spending rebound fails to materialize in 2015

02/23/2016  Recent capital spending trends indicative of maturing semiconductor industry.

Fairchild rejects proposal from China Resources, Hua Capital

02/18/2016  Fairchild Semiconductor's board of directors has determined that the unsolicited proposal received from China Resources Microelectronics Ltd and Hua Capital Management Co., Ltd. does not constitute a “Superior Proposal” as defined in the company’s agreement with ON Semiconductor.

Demand for semiconductor ICs fueling global wafer-level manufacturing equipment market through 2020

02/16/2016  According to the latest market study released by Technavio, the global wafer-level manufacturing equipment market is set to post a CAGR of over 4 percent by 2020.

EV Group joins IRT Nanoelec 3D Integration Program

02/11/2016  EVG joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies.

Yield and cost challenges at 16nm and beyond

02/08/2016  A new 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated.

TSMC assessing February 6 earthquakes and planning recovery

02/08/2016  TSMC this weekend announced that the earthquake of 6.4 magnitude which struck southern Taiwan at 3:57 am on February 6, 2016 did not cause any serious personnel injuries nor any structural or facility damage to the Company’s Fab 14 and Fab 6 manufacturing sites in the Tainan Science Park.

Wirelessly supplying power to brain

02/08/2016  A research team at the Department of Electrical and Electronic Information Engineering at Toyohashi University of Technology has developed a wafer-level packaging technique to integrate a silicon large-scale integration (LSI) chip in a very thin film of a thickness 10 μm.

Cautious expectations amid a slow-growth global economy

02/04/2016  The health of the IC industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong IC market growth without at least a “good” worldwide economy to support it.

Presto Engineering expands turnkey IC production management services with three new operations in Asia

02/02/2016  Presto Engineering Inc. announced this week that it has significantly expanded its turnkey capabilities with the opening of two new manufacturing hubs and a world-wide logistics center in Asia.

TowerJazz completes acquisition of Maxim's San Antonio fabrication facility

02/02/2016  TowerJazz, the global specialty foundry leader, announced today that it completed its previously announced acquisition of an 8-inch wafer fabrication facility in San Antonio, Texas, United States from Maxim Integrated Products, Inc.

Smart Equipment Technology joins IRT Nanoelec 3D Integration Program

01/15/2016  Will work with Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D die-to-wafer stacking technologies using direct Cu-Cu bonding

Advanced packaging industry: What's new on the market?

01/13/2016  The mobile sector is driving production and market growth; however a new market driver, IoT is on the horizon and is expected to have a significant impact on the advanced packaging industry.

Semiconductor capital spending to decline 4.7% in 2016, according to Gartner

01/12/2016  Worldwide semiconductor capital spending is projected to decline 4.7 percent in 2016, to $59.4 billion, according to Gartner, Inc.

Semiconductor capital spending market in the US to reach over $31B by 2019

01/11/2016  Technavio's market research analysts estimate the semiconductor capital spending market in the US, to grow at a CAGR of around 9% between 2015 and 2019.




TWITTER


WEBCASTS



Advanced Packaging: A Changing Landscape Rife with Opportunities

May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.

Sponsored By:
Trends in MEMS

May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Fan-Out Wafer Level Packaging

May 2016 (Date and time TBD) / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Sponsored By:
More Webcasts

TECHNOLOGY PAPERS



Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

Adhesives for Electronic Applications

Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,

More Technology Papers

EVENTS



SID Display Week 2016
San Francisco, CA
http://www.displayweek.org
May 22, 2016 - May 27, 2016
Design Automation Conference
Austin, TX
https://dac.com
June 05, 2016 - June 09, 2016
The ConFab
Las Vegas, NV
http://theconfab.com
June 12, 2016 - July 15, 2016
SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016

VIDEOS