Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



TSV integration is creating growth and significant interest in the equipment and materials industry

11/18/2014  The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.

TI to open 300mm wafer bumping facility in Chengdu, China

11/06/2014  Chengdu assembly/test facility now in production; site celebrates grand opening

SEMI extends ASMC Call for Papers deadline to November 10

10/30/2014  SEMI announced today that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 10.

IBM to pay GlobalFoundries $1.5B to take over chip fabs

10/20/2014  IBM and GLOBALFOUNDRIES today announced that GLOBALFOUNDRIES will acquire IBM's global commercial semiconductor technology business.

Growing momentum in semiconductor manufacturing in Vietnam

10/17/2014  The 2nd annual SEMI Vietnam Semiconductor Strategy Summit, co-organized with the Saigon Hi-Tech Park and with FabMax as the premier sponsor, was held September 16-17, 2014 in Ho Chi Minh City.

Semiconductor market in India is expected to reach US$ 52.58B by 2020

10/14/2014  India has a very large industry base of electronics items, but there is little manufacturing base for semiconductors.

Mentor Graphics wins $36M in patent infringement suit

10/13/2014  A Portland, Oregon jury today delivered a verdict in favor of Mentor Graphics in a patent infringement trial against Synopsys, Inc., awarding Mentor Graphics $35 million in damages and royalties.

FlipChip International creates 250 multi-product wafer bump designs

10/01/2014  FlipChip International (FCI), the global technology leader in flip chip bumping and advanced wafer level packaging, announced that their engineering team had completed design and production of the 250th Multi-Product Wafer Bump design since January 2013.

NANIUM launches the industry’s largest WLCSP in volume production

09/23/2014  NANIUM today announced it has successfully launched the industry’s largest Wafer-Level Chip Scale Package (WLCSP) in volume.

Fermilab implements Ziptronix's DBI hybrid bonding in high-end 3D image sensors

09/09/2014  Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments.

STATS ChipPAC’s fcCuBE technology surpasses 100 million unit milestone

08/20/2014  STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

MEMSIC introduces the world's first monolithic and wafer level packaged 3D-axis accelerometer

08/15/2014  MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world's first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology.

Pfeiffer Vacuum joins the Facilities 450mm Consortium

08/06/2014  The Facilities 450mm Consortium (F450C), a partnership of leading nanoelectronics facility companies guiding the effort to design and build the next-generation 450mm computer chip fabrication facilities, today announced it has again increased in size, naming Pfeiffer Vacuum as the twelfth member company to join the consortium.

Fusion bonding for next-generation 3D-ICs

07/24/2014  Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.

Jordan Valley Semiconductors wins more market share in advanced wafer level packaging

07/03/2014  Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, today announced that its micro-spot X-ray Fluorescence (µXRF) metrology tool has been qualified for production monitoring of advanced Wafer Level Packaging (WLP) processes, by another memory player.

ConFab panelists discuss optimizing R&D in the changing semi landscape

06/24/2014  Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

Noise cancellation: The new failure and yield analysis superpower

06/22/2014  Root cause deconvolution is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone.

Applied Materials enables cost-effective vertical integration of 3D chips

05/28/2014  Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

STATS ChipPAC introduces robust encapsulated wafer level packaging technology

05/28/2014  STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

Ziptronix and EV Group demonstrate submicron accuracies for wafer-to-wafer hybrid bonding

05/27/2014  ­ Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers.




FINANCIALS



TECHNOLOGY PAPERS



Enhancing the Reliability of Flip Chip Assemblies with Underfill Encapsulants

The development of epoxy based underfill encapsulants marked a turning point for flip chip technology, and the semiconductor industry. Underfill encapsulants are carefully formulated to ensure flowability, an acceptable CTE, and other desirable properties. In this white paper, we explore what properties are required for effective underfills to ensure reliability and quality in flip chip applications.October 07, 2014
Sponsored by Master Bond, Inc.,

Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Root Cause Deconvolution (RCD), a statistical enhancement technology recently made available in Mentor Graphics’ Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout-aware diagnosis reports together to identify the underlying defect distribution (root cause distribution) that is most likely to explain this set of diagnosis results. The results are then back- annotated to the individual diagnosis suspects.April 24, 2014
Sponsored by Mentor Graphics

More Technology Papers

WEBCASTS



Extending Moore's Law

January 2014 (Date and time TBD)

Will IC capability, affordability and diversity continue to grow on a Moore’s Law cadence? Will our ability to make ICs denser and transistors smaller and cheaper slow down any time soon? Intel's Yan Borodovsky will discuss multiple path ahead for the industry to continue Moore’s Law for years to come, from the lithographer's perspective.

Sponsored By:

How the IoT is Driving Semiconductor Technology

January 2014 (Date and time TBD)

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.

Sponsored By:
FinFETs

February 2014 (Date and time TBD)

FinFETs provide better performance than planar transistor architectures, but the entire 3D structure requires strict process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. As more advanced node semiconductors enter production, the application of HKMG will be key to yield and cost improvement. Advanced wafer fab tools are needed for HKMG, such as ALD.

Sponsored By:

More Webcasts

VIDEOS



EVENTS



2014 IEEE International Electron Device Meeting
San Francisco, CA
http://www.his.com/~iedm/
December 15, 2014 - December 17, 2014
International Strategy Symposium 2015
Half Moon Bay, CA
http://www.semi.org/en/node/35136
January 11, 2015 - January 14, 2015
European 3D TSV Summit
Grenoble, France
http://www.semi.org/eu/node/8566
January 19, 2015 - January 21, 2015
SEMICON Korea 2015
Seoul, Korea
http://www.semiconkorea.org/en/
February 04, 2015 - February 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015