Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



NANIUM launches the industry’s largest WLCSP in volume production

09/23/2014  NANIUM today announced it has successfully launched the industry’s largest Wafer-Level Chip Scale Package (WLCSP) in volume.

SPIE Photomask Technology Wrap-up

09/23/2014  Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

SPIE panel tackles mask complexity issues

09/19/2014  Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

ASML on EUV: Available at 10nm

09/17/2014  Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Design and Manufacturing Technology Development in Future IC Foundries

09/16/2014  Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem.

Monolithic 3D breakthrough at IEEE S3S 2014

09/15/2014  In the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

Process Watch: Sampling matters

09/15/2014  Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.

Foundry, EDA partnership eases move to advanced process nodes

09/15/2014  A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.

Research Alert: September 9, 2014

09/09/2014  GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential

Fermilab implements Ziptronix's DBI hybrid bonding in high-end 3D image sensors

09/09/2014  Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments.

The Week in Review: September 5, 2014

09/05/2014  New non-volatile memory technology; President and CEO of FSA announced; Samsung to use ProPlus 14nm finFET SPICE modeling platform; MEMS gyroscope from Analog Devices; SEMICON Taiwan held this week

Research Alert: September 3, 2014

09/03/2014  A new, tunable device for spintronics; Copper shines as flexible conductor; Competition for graphene

Intel Announces “New Interconnect” for 14nm

09/02/2014  Intel has just announced that “Embedded Multi-die Interconnect Bridge (EMIB”) packaging technology will be available to 14nm foundry customers.

The Week in Review: August 29, 2014

08/29/2014  Intel releases new packaging technologies; Fairchild Semiconductor to close two facilities; KLA-Tencor introduces new metrology tools; UMC joins Fujitsu's new foundry company; Thinnest-possible semiconductor; SEMI announces keynotes for Vietnam Semiconductor Strategy Summit

Lithography: What are the alternatives to EUV?

08/28/2014  Hopes remain high for EUV, but long delays has caused attention to shift to various alternatives.

The Week in Review: August 22, 2014

08/22/2014  Collaboration for next-generation smart glasses; Book-to-bill ratio holds steady in July; Intel and Unity to collaborate; MediaTek launches new R&D facility; Amkor appoints new member to board of directors; STATS ChipPAC achieves shipping milestone

STATS ChipPAC’s fcCuBE technology surpasses 100 million unit milestone

08/20/2014  STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

The Week in Review: August 15, 2014

08/15/2014  The growing semiconductor market in India; MEMSIC's monolithic, wafer-level packaged accelerometer; Si2 adds new director of 3DIC Programs; Worldwide silicon wafer area shipments increased during the second quarter 2014; LightFair announces Call for Speakers

MEMSIC introduces the world's first monolithic and wafer level packaged 3D-axis accelerometer

08/15/2014  MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world's first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology.

Pfeiffer Vacuum joins the Facilities 450mm Consortium

08/06/2014  The Facilities 450mm Consortium (F450C), a partnership of leading nanoelectronics facility companies guiding the effort to design and build the next-generation 450mm computer chip fabrication facilities, today announced it has again increased in size, naming Pfeiffer Vacuum as the twelfth member company to join the consortium.




HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Root Cause Deconvolution (RCD), a statistical enhancement technology recently made available in Mentor Graphics’ Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout-aware diagnosis reports together to identify the underlying defect distribution (root cause distribution) that is most likely to explain this set of diagnosis results. The results are then back- annotated to the individual diagnosis suspects.April 24, 2014
Sponsored by Mentor Graphics

UV LED Curing for the Electronics Industry

This paper provides an introduction to UV LED curing and the many benefits UV LED curing provides for bonding and coating applications in the electronics industry. Product manufacturers, machine builders, and chemistry formulators will gain an understanding of the benefits and how to apply UV LED curing in manufacturing processes. Included are specific examples of how manufacturers are using UV LED to make touch screens, mobile phones, micro speakers, and hard disk drives.April 03, 2014
Sponsored by Phoseon Technology

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WEBCASTS



Advanced Packaging

Oct. 2014 (Date and time TBD)

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.

Sponsored By:
Metrology

Oct. 2014 (date and time TBD)

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.

Sponsored By:

Interconnects

Oct. 2014 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:

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