Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Many mixes to match litho apps

04/29/2016  The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

Leti's CoolCube 3D Transistor Stacking Improves with Qualcomm Help

04/27/2016  Collaborating to build out design to fabrication ecosystem.

Roll-to-Roll Coating Technology: It's a Different Ball of Wax

04/18/2016  Manufacturing flexible electronics and coatings for a variety of products has some similarities to semiconductor manufacturing and some substantial differences, principally roll-to-roll fabrication, as opposed to making chips on silicon wafers and other rigid substrates. This interview is with Neil Morrison, senior manager, Roll-to-Roll Coating Products Division, Applied Materials.

IoT Demands Part 2: Test and Packaging

04/15/2016  To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes.

IoT Demands Part 1: EDA and Fab Nodes

04/14/2016  To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness.

The advanced packaging industry has reached its zenith

04/14/2016  To overcome the current market and technology constraints taking place today within the semiconductor industry, new advanced packaging technologies have been developed by industrial companies.

Presto Engineering and Peraso Technologies Develop Innovative Test Solution for 60 GHz Transceiver

04/12/2016  Presto Engineering Inc., a world leader in semiconductor product engineering and supply chain management, and Peraso Technologies, a leading wireless chipset manufacturer, today jointly announced their successful collaboration in developing a comprehensive test solution for Peraso’s recently-launched 60 GHz semiconductor products.

Cadence to Acquire Rocketick

04/11/2016  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has entered into a definitive agreement to acquire Rocketick Technologies Ltd.

Mentor Graphics U2U Meeting April 26 in Santa Clara

04/11/2016  Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Cadence and University of Oxford Foster the Advancement of Formal Verification Innovation

04/07/2016  Cadence Design Systems, Inc. and the University of Oxford today announced a move to foster the advancement of formal verification innovation with the appointment of Dr. Ziyad Hanna, Cadence vice president of R&D, as a visiting professor in Oxford's Department of Computer Science for the next three years.

Worldwide semiconductor wafer-level manufacturing equipment market declined 1% in 2015

04/06/2016  Worldwide semiconductor wafer-level manufacturing equipment revenue totaled $33.6 billion in 2015, a 1 percent decline from 2014, according to final results by Gartner, Inc.

Synopsys Debuts Tools at Users Group Meeting

03/30/2016  Aart de Geus, the chairman and co-chief executive officer of Synopsys, used his keynote address at the 2016 Synopsys Users Group conference in Silicon Valley to tout a pair of new products.

Texas Instruments names Devan Iyer Vice President

03/29/2016  Texas Instruments Incorporated (TI) announced that Devan Iyer has been elected vice president of the company.

3D Chips, New Packaging Challenge Metrology and Inspection Gear

03/21/2016  Metrology and inspection technology is growing more complicated as device dimensions continue to shrink. Discussing crucial trends in the field are Lior Engel, vice president of the Imaging and Process Control Group at Applied Materials, and Rudolph Technologies.

Molecular Modeling of Materials Defects for Yield Recovery

03/21/2016  New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor ICs, while old materials are being extended with more stringent specifications.

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

03/17/2016  Mentor Graphics Corporation today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification.

Linde Supports New Wave of PV Plants in SE Asia

03/17/2016  The Linde Group supports the expansion of photovoltaic solar cell manufacturing in Southeast Asia by offering its full portfolio of gases and wet chemicals, along with engineering services, to help the new PV cell plants being established in the region.

New MEMS Design Contest Encourages Advances in MEMS Technology

03/16/2016  Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016.

Mentor Graphics Adds Support for Integrated Fan-Out (InFO) Packaging Technology at TSMC

03/14/2016  Mentor Graphics Corporation today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology.

2015 European SEMI Award honors Paul Lindner

03/08/2016  Paul Lindner, executive technology director at EV Group, is the recipient of the 2015 European SEMI Award.




TWITTER


WEBCASTS



Advanced Packaging: A Changing Landscape Rife with Opportunities

May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.

Sponsored By:
Trends in MEMS

May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Fan-Out Wafer Level Packaging

May 2016 (Date and time TBD) / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Sponsored By:
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TECHNOLOGY PAPERS



Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

Adhesives for Electronic Applications

Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,

More Technology Papers

EVENTS



SID Display Week 2016
San Francisco, CA
http://www.displayweek.org
May 22, 2016 - May 27, 2016
Design Automation Conference
Austin, TX
https://dac.com
June 05, 2016 - June 09, 2016
The ConFab
Las Vegas, NV
http://theconfab.com
June 12, 2016 - July 15, 2016
SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016

VIDEOS