Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



TSV integration is creating growth and significant interest in the equipment and materials industry

11/18/2014  The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.

TI to open 300mm wafer bumping facility in Chengdu, China

11/06/2014  Chengdu assembly/test facility now in production; site celebrates grand opening

Experts at the Table: Focus on Semiconductor Materials

11/03/2014  The cutting edge in semiconductor manufacturing has meant not only big changes in IC design and process technology, but also in semiconductor materials. Experts weigh in from Linde Electronics; Kate Wilson of Edwards Vacuum; David Thompson of Applied Materials; and Ed Shober of Air Products and Chemicals.

Air-gaps in Copper Interconnects for Logic

10/31/2014  Intel’s “14nm-node” process uses air-gaps in dielectrics; direction disclosed four years ago.

SEMI extends ASMC Call for Papers deadline to November 10

10/30/2014  SEMI announced today that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 10.

IBM to pay GlobalFoundries $1.5B to take over chip fabs

10/20/2014  IBM and GLOBALFOUNDRIES today announced that GLOBALFOUNDRIES will acquire IBM's global commercial semiconductor technology business.

Growing momentum in semiconductor manufacturing in Vietnam

10/17/2014  The 2nd annual SEMI Vietnam Semiconductor Strategy Summit, co-organized with the Saigon Hi-Tech Park and with FabMax as the premier sponsor, was held September 16-17, 2014 in Ho Chi Minh City.

Deeper Dive -- Mentor Graphics Looks to the Future

10/14/2014  There has been a great deal of handwringing and naysaying about the industry’s progress to the 14/16-nanometer process node, along with wailing and gnashing of teeth about the slow progress of extreme-ultraviolet lithography, which was supposed to ease the production of 14nm or 16nm chips. Joseph Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division, is having none of it.

Semiconductor market in India is expected to reach US$ 52.58B by 2020

10/14/2014  India has a very large industry base of electronics items, but there is little manufacturing base for semiconductors.

Mentor Graphics wins $36M in patent infringement suit

10/13/2014  A Portland, Oregon jury today delivered a verdict in favor of Mentor Graphics in a patent infringement trial against Synopsys, Inc., awarding Mentor Graphics $35 million in damages and royalties.

FlipChip International creates 250 multi-product wafer bump designs

10/01/2014  FlipChip International (FCI), the global technology leader in flip chip bumping and advanced wafer level packaging, announced that their engineering team had completed design and production of the 250th Multi-Product Wafer Bump design since January 2013.

NANIUM launches the industry’s largest WLCSP in volume production

09/23/2014  NANIUM today announced it has successfully launched the industry’s largest Wafer-Level Chip Scale Package (WLCSP) in volume.

SPIE Photomask Technology Wrap-up

09/23/2014  Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

SPIE panel tackles mask complexity issues

09/19/2014  Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

ASML on EUV: Available at 10nm

09/17/2014  Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Design and Manufacturing Technology Development in Future IC Foundries

09/16/2014  Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem.

Monolithic 3D breakthrough at IEEE S3S 2014

09/15/2014  In the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

Process Watch: Sampling matters

09/15/2014  Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.

Foundry, EDA partnership eases move to advanced process nodes

09/15/2014  A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.

Research Alert: September 9, 2014

09/09/2014  GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential




FINANCIALS



TECHNOLOGY PAPERS



Enhancing the Reliability of Flip Chip Assemblies with Underfill Encapsulants

The development of epoxy based underfill encapsulants marked a turning point for flip chip technology, and the semiconductor industry. Underfill encapsulants are carefully formulated to ensure flowability, an acceptable CTE, and other desirable properties. In this white paper, we explore what properties are required for effective underfills to ensure reliability and quality in flip chip applications.October 07, 2014
Sponsored by Master Bond, Inc.,

Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Root Cause Deconvolution (RCD), a statistical enhancement technology recently made available in Mentor Graphics’ Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout-aware diagnosis reports together to identify the underlying defect distribution (root cause distribution) that is most likely to explain this set of diagnosis results. The results are then back- annotated to the individual diagnosis suspects.April 24, 2014
Sponsored by Mentor Graphics

More Technology Papers

WEBCASTS



Extending Moore's Law

January 2014 (Date and time TBD)

Will IC capability, affordability and diversity continue to grow on a Moore’s Law cadence? Will our ability to make ICs denser and transistors smaller and cheaper slow down any time soon? Intel's Yan Borodovsky will discuss multiple path ahead for the industry to continue Moore’s Law for years to come, from the lithographer's perspective.

Sponsored By:

How the IoT is Driving Semiconductor Technology

January 2014 (Date and time TBD)

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.

Sponsored By:
FinFETs

February 2014 (Date and time TBD)

FinFETs provide better performance than planar transistor architectures, but the entire 3D structure requires strict process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. As more advanced node semiconductors enter production, the application of HKMG will be key to yield and cost improvement. Advanced wafer fab tools are needed for HKMG, such as ALD.

Sponsored By:

More Webcasts

VIDEOS



EVENTS



2014 IEEE International Electron Device Meeting
San Francisco, CA
http://www.his.com/~iedm/
December 15, 2014 - December 17, 2014
International Strategy Symposium 2015
Half Moon Bay, CA
http://www.semi.org/en/node/35136
January 11, 2015 - January 14, 2015
European 3D TSV Summit
Grenoble, France
http://www.semi.org/eu/node/8566
January 19, 2015 - January 21, 2015
SEMICON Korea 2015
Seoul, Korea
http://www.semiconkorea.org/en/
February 04, 2015 - February 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015