Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Texas Instruments names Devan Iyer Vice President

03/29/2016  Texas Instruments Incorporated (TI) announced that Devan Iyer has been elected vice president of the company.

3D Chips, New Packaging Challenge Metrology and Inspection Gear

03/21/2016  Metrology and inspection technology is growing more complicated as device dimensions continue to shrink. Discussing crucial trends in the field are Lior Engel, vice president of the Imaging and Process Control Group at Applied Materials, and Rudolph Technologies.

Molecular Modeling of Materials Defects for Yield Recovery

03/21/2016  New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor ICs, while old materials are being extended with more stringent specifications.

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

03/17/2016  Mentor Graphics Corporation today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification.

Linde Supports New Wave of PV Plants in SE Asia

03/17/2016  The Linde Group supports the expansion of photovoltaic solar cell manufacturing in Southeast Asia by offering its full portfolio of gases and wet chemicals, along with engineering services, to help the new PV cell plants being established in the region.

New MEMS Design Contest Encourages Advances in MEMS Technology

03/16/2016  Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016.

Mentor Graphics Adds Support for Integrated Fan-Out (InFO) Packaging Technology at TSMC

03/14/2016  Mentor Graphics Corporation today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology.

2015 European SEMI Award honors Paul Lindner

03/08/2016  Paul Lindner, executive technology director at EV Group, is the recipient of the 2015 European SEMI Award.

Many Mixes to Match Litho Apps

03/03/2016  "Mix and Match" has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing.

BiTS: The ever-shrinking package underscores emerging challenges and solutions

02/25/2016  What’s the single area that is being most disrupted by emergent technologies like the Internet of Things (or the Internet of Vehicles) and Silicon Photonics? We think it’s packaging.

Design-for-Testability (DFT) Verified with Hardware Emulation

02/25/2016  Several years ago, while at Automatic Test Equipment (ATE) leader Teradyne, I witnessed frequent debates on a fundamental dilemma: On the production/testing floor, is it better to pass a failing device or reject a good device?

What’s the Next-Gen Litho Tech? Maybe All of Them

02/25/2016  The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race.

Laser Suppliers Move Past the Neon Gas Crisis

02/24/2016  That neon gas shortage? So 2015.

Canon, Toshiba Join eBeam Initiative Group

02/24/2016  The eBeam Initiative announced that Canon and Toshiba are new members of the industry organization.

Semiconductor capital spending rebound fails to materialize in 2015

02/23/2016  Recent capital spending trends indicative of maturing semiconductor industry.

What to See at the SPIE Advanced Lithography Show

02/22/2016  The SPIE Advanced Lithography conference, from Tuesday, February 23, to Thursday, February 25, offers an incredible amount of technical information in a few long, fun days.

Fairchild rejects proposal from China Resources, Hua Capital

02/18/2016  Fairchild Semiconductor's board of directors has determined that the unsolicited proposal received from China Resources Microelectronics Ltd and Hua Capital Management Co., Ltd. does not constitute a “Superior Proposal” as defined in the company’s agreement with ON Semiconductor.

Demand for semiconductor ICs fueling global wafer-level manufacturing equipment market through 2020

02/16/2016  According to the latest market study released by Technavio, the global wafer-level manufacturing equipment market is set to post a CAGR of over 4 percent by 2020.

EV Group joins IRT Nanoelec 3D Integration Program

02/11/2016  EVG joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies.

Yield and cost challenges at 16nm and beyond

02/08/2016  A new 5D solution utilizes multiple types of metrology systems to identify and control fab-wide sources of pattern variation, with an intelligent analysis system to handle the data being generated.




TWITTER


WEBCASTS



Interconnection Technologies

June 2016 (Date and time TBD)/ Sponsored by Air Products

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:
Is the Semiconductor Industry Ready for Industry 4.0 and the IIoT?

June 2016 (Date and time TBD)/ Sponsored by Epicor and Siemens

An industrial revolution is in the making, equivalent some say to the introduction of steam power at the tail end of the 18th century. Known as smart manufacturing, Industry 4.0 (after the German initiative Industrie 4.0), the industrial internet of things (IIoT), or simply the fourth industrial revolution, the movement will radically change how manufacturing is done. Greater connectivity and information sharing -- enabled by new capabilities in data analytics, remote monitoring and mobility -- will lead to increased efficiency and reduced costs. There will be a paradigm shift from “centralized” to “decentralized” production. Semiconductor manufacturing has long been thought of as the most advanced manufacturing process in the world, but it’s not clear if long-held beliefs about how proprietary data, such as process recipes, are managed. Industry experts will examine the potential for the semiconductor factory of the future, and discuss potential roadblocks.

Sponsored By:
More Webcasts

TECHNOLOGY PAPERS



Specialized Materials Meet Critical Packaging Needs in MEMS Devices

Microelectromechanical systems (MEMS) present both unique market opportunities and significant manufacturing challenges for product designers in nearly every application segment. Used as accelerometers, pressure sensors, optical devices, microfluidic devices, and more, these microfabricated sensors and actuators often need to be exposed to the environment, but also need to be protected from environmental factors. Although standard semiconductor manufacturing methods provide a baseline capability in meeting these challenges, the unique requirements of MEMS devices drive a need for specialized epoxies and adhesives able to satisfy often-conflicting demands.May 12, 2016
Sponsored by Master Bond, Inc.,

Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

More Technology Papers

EVENTS



SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016
SEMICON Europa 2016
Grenoble, France
http://www.semiconeuropa.org
October 25, 2016 - October 27, 2016

VIDEOS