Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Embedded die in substrate: Challenges are still ahead

03/03/2015  Embedded die in substrate: what are the next steps for the growth?

Freescale and NXP agree to $40 Billion merger

03/03/2015  Chipmaker NXP Semiconductors NV announced Sunday night that it has agreed to buy Freescale Semiconductor Ltd for $11.8 billion and merge business operations.

SPIE Advanced Lithography conference concludes

02/27/2015  Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Learning to live with negative tone

02/27/2015  In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.

Directed Self Assembly Hot Topic at SPIE

02/25/2015  At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.

Proponents of EUV, immersion lithography face off at SPIE

02/25/2015  The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium. EUVt lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and TSMC. On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

Fan-Out Wafer Level Packaging: With a $200M market in 2015, Yole is expecting 30% CAGR in the coming years

02/24/2015  “Fan-Out Wafer Level Packaging (FOWLP) is already in high-volume” announces Yole Développement (Yole) in its new report, Fan-Out and Embedded Die: Technologies & Market. According to Yole’s analysts, FOWLP market reaches almost $200M in 2015.

SPIE plenary takes in photonics, 3DICs, connected devices

02/23/2015  Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.

Complexity is the Theme at Lithography Conference

02/23/2015  Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.

Penn researchers develop new technique for making molybdenum disulfide

02/20/2015  University of Pennsylvania researchers have made an advance in manufacturing one such material, molybdenum disulphide.

Qualcomm and China's National Development and Reform Commission reach resolution

02/09/2015  Qualcomm Incorporated today announced that it has reached a resolution with China's National Development and Reform Commission (NDRC) regarding the NDRC's investigation of Qualcomm under China's Anti-Monopoly Law.

SEMICON Show Highlights Chip Manufacturing in South Korea

02/04/2015  The SEMICON Korea conference and exhibition opens Wednesday in Seoul for a three-day run. The show highlights the importance of semiconductor manufacturing in South Korea, home to two of the biggest memory chip makers in the world, Samsung Electronics and SK Hynix.

"The Electrical Arts" and the First Trans-Atlantic Telegraph Cable

01/28/2015  Before there were electrical engineers and standard definitions for the ampere, ohm and volt, entrepreneurs and scientists in the United Kingdom and the United States worked on the issue of improving communications between the Old World and the New World.

2015 outlook: Tech trends and drivers

01/20/2015  Leading industry experts provide their perspectives on what to expect in 2015. 3D devices and 3D integration, rising process complexity and “big data” are among the hot topics.

Amkor Technology announces settlement with Tessera

01/15/2015  Amkor Technology, Inc. today announced the settlement of its outstanding litigation and arbitration proceedings with Tessera, Inc.

Orbotech announces collaboration between SPTS and Fraunhofer on process development of wafer level packaging

01/15/2015  Orbotech Ltd. today announced that SPTS Technologies is collaborating with Fraunhofer IZM, an international institute specializing in applied and industrial contract research, on next generation wafer level packaging of microelectronic devices.

JEOL and UC Irvine partner to develop electron microscopy and materials research center

01/14/2015  JEOL USA and the University of California's Irvine Materials Research Institute (IMRI) have entered into a strategic partnership to create a premier electron microscopy and materials science research facility.

MEMSensing launches the world's smallest commercial 3-axis accelerometer with SMIC

01/05/2015  MEMSensing Microsystems Co. and Semiconductor Manufacturing International Corporation jointly announced the launch of the world's smallest 3-axis accelerometer MSA330, which utilizes SMIC's CMOS integrated MEMS device fabrication and TSV-based wafer level packaging technologies.

Solid Doping for Bulk FinFETs

01/05/2015  In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing.

Global semiconductor market set for strongest growth in four years in 2014

12/23/2014  Worldwide semiconductor market revenue is on track to achieve a 9.4 percent expansion this year, with broad-based growth across multiple chip segments driving the best industry performance since 2010.




HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



ASIC Design Made Cost Effective with Low Cost Tools and Masks

For smaller projects or companies with modest design budgets, ASIC design is becoming a viable option due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs. April 13, 2015
Sponsored by Mentor Graphics

High-Performance Analog and RF Circuit Simulation

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.March 13, 2015
Sponsored by Mentor Graphics

How to Use Imaging Colorimeters for FPD Automated Visual Inspection

The use of imaging colorimeter systems and analytical software to assess display brightness and color uniformity, contrast, and to identify defects in FPDs is well established. A fundamental difference between imaging colorimetry and traditional machine vision is imaging colorimetry's accuracy in matching human visual perception for light and color uniformity. This white paper describes how imaging colorimetry can be used in a fully-automated testing system to identify and quantify defects in high-speed, high-volume production environments.February 27, 2015
Sponsored by Radiant Vision Systems

More Technology Papers

WEBCASTS



3D Integration: The Most Effective Path for Future IC Scaling

Thursday, April 23, 2015 at 12:00 p.m. EST

It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.

Sponsored By:
Trends in Materials: The Smartphone Driver

Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.

Sponsored By:
MEMS

May 2015 (Date and time TBD)

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
More Webcasts

VIDEOS



EVENTS



SEMICON Southeast Asia 2015
Penang, Malaysia
http://www.semiconsea.org
April 22, 2015 - April 24, 2015
ASMC 2015
Saratoga Springs, NY
http://www.semi.org/en/asmc2015
May 03, 2015 - May 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015
65th Annual ECTC
San Diego, CA
http://www.ectc.net
May 26, 2015 - May 29, 2015
SID Display Week 2015
San Jose, California
http://www.displayweek.org
May 31, 2015 - June 05, 2015