Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Orbotech announces collaboration between SPTS and Fraunhofer on process development of wafer level packaging

01/15/2015  Orbotech Ltd. today announced that SPTS Technologies is collaborating with Fraunhofer IZM, an international institute specializing in applied and industrial contract research, on next generation wafer level packaging of microelectronic devices.

JEOL and UC Irvine partner to develop electron microscopy and materials research center

01/14/2015  JEOL USA and the University of California's Irvine Materials Research Institute (IMRI) have entered into a strategic partnership to create a premier electron microscopy and materials science research facility.

MEMSensing launches the world's smallest commercial 3-axis accelerometer with SMIC

01/05/2015  MEMSensing Microsystems Co. and Semiconductor Manufacturing International Corporation jointly announced the launch of the world's smallest 3-axis accelerometer MSA330, which utilizes SMIC's CMOS integrated MEMS device fabrication and TSV-based wafer level packaging technologies.

Solid Doping for Bulk FinFETs

01/05/2015  In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing.

Global semiconductor market set for strongest growth in four years in 2014

12/23/2014  Worldwide semiconductor market revenue is on track to achieve a 9.4 percent expansion this year, with broad-based growth across multiple chip segments driving the best industry performance since 2010.

IoT's divergent needs will drive different types of technologies

12/19/2014  Given the current buzz around the Internet of Things (IoT), it is easy to lose sight of the challenges – both economic and technical.

The most expensive defect

12/18/2014  Defects that aren’t detected inline cost fabs the most.

From transistors to bumps: Preparing SEM cross-sections by combining site-specific cleaving and broad ion milling

12/18/2014  Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

IEDM: Thanks for MEMS-ories

12/16/2014  At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.

Amkor Technology licenses proprietary copper pillar wafer bump technology to GLOBALFOUNDRIES

12/16/2014  Amkor Technology, Inc., a provider of semiconductor assembly and test services, today announced that it has granted GLOBALFOUNDRIES a non-exclusive license to its proprietary copper pillar wafer bump technology.

Innovation in the shadow of volcanic change

12/16/2014  The semiconductor equipment and materials industry is currently enjoying a double-digit annual growth rate and good prospects looking forward to 2015.

Global Semiconductor Alliance announces 2014 Award recipients

12/12/2014  GSA members identified the Most Respected Public Semiconductor Company Award winners by casting ballots for the industry’s most respected companies for its products, vision and future opportunities.

System Plus analyzes the world's smallest microbolometer-based thermal imaging camera core released by FLIR

12/11/2014  Initially focused on the military, uncooled thermal camera sales have grown significantly due to substantial cost reduction of micro bolometers and growing adoption in commercial markets, including thermography, automotive and surveillance applications.

Mentor Graphics Announces New Verification IP for PCIe 4.0

12/08/2014  Mentor Graphics Corp. announced the immediate availability of its new Mentor EZ-VIP PCI Express Verification IP, which reduces testbench assembly time for ASIC and FPGA design verification by a factor of up to 10X.

Applied Materials Introduces New Hardmask Process, Saphira

11/24/2014  A new hardmask material, called Saphira, and accompanying processes was introduced Applied Materials. The material, which is transparent and offers high selectivity and good mechanical strength, could reduce manufacturing costs by 35% per module.

NFC IGZO TFT for Game Cards

11/20/2014  Holst Centre, imec, and Cartamundi work on flexible Near Field Communication tags embedded in paper cards.

TSV integration is creating growth and significant interest in the equipment and materials industry

11/18/2014  The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.

TI to open 300mm wafer bumping facility in Chengdu, China

11/06/2014  Chengdu assembly/test facility now in production; site celebrates grand opening

Experts at the Table: Focus on Semiconductor Materials

11/03/2014  The cutting edge in semiconductor manufacturing has meant not only big changes in IC design and process technology, but also in semiconductor materials. Experts weigh in from Linde Electronics; Kate Wilson of Edwards Vacuum; David Thompson of Applied Materials; and Ed Shober of Air Products and Chemicals.

Air-gaps in Copper Interconnects for Logic

10/31/2014  Intel’s “14nm-node” process uses air-gaps in dielectrics; direction disclosed four years ago.




HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



Silicones Meet the Needs of the Electronics Industry

Remarkable silicones. The combination of their unique ability to maintain physical properties across a wide range of temperature, humidity, and frequency--combined with their flexibility--set them apart. Silicone based adhesives, sealants, potting and encapsulation compounds are used in hundreds of consumer, business, medical, and military electronic systems. In this white paper, learn what makes silicones different from other organic polymers, why their properties remain stable across different temperatures, and how they have played a major role in the rapid innovation of the electronics industry.May 12, 2015
Sponsored by Master Bond, Inc.,

ASIC Design Made Cost Effective with Low Cost Tools and Masks

For smaller projects or companies with modest design budgets, ASIC design is becoming a viable option due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs. April 13, 2015
Sponsored by Mentor Graphics

High-Performance Analog and RF Circuit Simulation

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.March 13, 2015
Sponsored by Mentor Graphics

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WEBCASTS



Sensor Fusion and the Role of MEMS in IoT

Thursday May 28, 2015 at 1:00 p.m. EST

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Interconnects

June 2015 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:
Understanding Defects

July 2015 (Date and time TBD)

Yield improvement and production engineers working on today's ICs encounter many challenges as defects affecting device operation go undetected by traditional in-line techniques. Electrical Failure Analysis (EFA) is a suite of techniques that helps the modern day fab increase yields by isolating faults to areas small enough for Physical Failure Analysis (PFA). In this Webinar, we showcase a few of the proven EFA fault isolation techniques and describe how EFA helps to characterize the underlying defects.

Sponsored By:
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VIDEOS



EVENTS



SID Display Week 2015
San Jose, California
http://www.displayweek.org
May 31, 2015 - June 05, 2015
Design Automation Conference (DAC)
San Francisco, CA
https://dac.com
June 07, 2015 - June 11, 2015
SEMICON West 2015
San Francisco, CA
http://www.semiconwest.org
July 14, 2015 - July 16, 2015
SPIE Optics and Photonics
San Diego, CA
http://spie.org/x30491.xml
August 09, 2015 - August 13, 2015
European MEMS Summit
Milan, Italy
http://www.semi.org/eu/node/8871
September 17, 2015 - September 18, 2015
SPIE Photomask Technology 2015
Monterey, CA
http://spie.org/x6323.xml
September 29, 2015 - October 01, 2015