Wafer Processing

WAFER PROCESSING ARTICLES



Managing hazardous process exhausts in high volume manufacturing

03/30/2016  Integrated sub-fab systems allow HVM fab operators to safely and efficiently implement new processes containing hazardous process chemicals.

Chipmakers seek solution to neon gas supply shortage

03/30/2016  Finding a short term solution to the neon gas shortage problem will be challenging.

ACM demonstrates damage-free cleaning technology on 1Xnm patterned wafer

03/28/2016  ACM Research (Shanghai), Inc. has announced that it has solved the problem of patterned wafer cleaning.

TSMC and Nanjing sign 12-inch fab investment agreement

03/28/2016  TSMC today announced that the Company and the municipal government of Nanjing, China have signed an investment agreement.

How finFETs ended the service contract of silicide process

03/25/2016  A look into how the silicide process has evolved over the years, trying to cope with the progress in scaling technology and why it could no longer be of service to finFET devices.

Trace metal contamination: Choosing elastomer materials for critical operations

03/25/2016  An exploration of where trace metals come from, the impact they have on the industry and what can be done to reduce the risks.

3D Chips, New Packaging Challenge Metrology and Inspection Gear

03/21/2016  Metrology and inspection technology is growing more complicated as device dimensions continue to shrink. Discussing crucial trends in the field are Lior Engel, vice president of the Imaging and Process Control Group at Applied Materials, and Rudolph Technologies.

Molecular Modeling of Materials Defects for Yield Recovery

03/21/2016  New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor ICs, while old materials are being extended with more stringent specifications.

IRT Nanoelec project integrates laser directly on silicon with a modulator

03/18/2016  IRT Nanoelec today announced the first co-integration of a III-V/silicon laser and silicon Mach Zehnder modulator demonstrating 25 Gbps transmission on a single channel.

Process Watch: Reducing production costs with process control

03/18/2016  Adding process control reduces production costs and cycle time.

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

03/17/2016  Mentor Graphics Corporation today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification.

Linde Supports New Wave of PV Plants in SE Asia

03/17/2016  The Linde Group supports the expansion of photovoltaic solar cell manufacturing in Southeast Asia by offering its full portfolio of gases and wet chemicals, along with engineering services, to help the new PV cell plants being established in the region.

New MEMS Design Contest Encourages Advances in MEMS Technology

03/16/2016  Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016.

Cadence design tools certified for TSMC 7nm design starts and 10nm production

03/16/2016  Cadence Design Systems, Inc. today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process.

2016 semiconductor sales to go negative, says Semico Research

03/15/2016  After analyzing current trends, Semico announced the semiconductor industry is repeating the pattern from 2011-2012, albeit at a muted level.

SEMI reports 2015 global semiconductor equipment sales of $36.5B

03/15/2016  SEMI today reported that worldwide sales of semiconductor manufacturing equipment totaled $36.53 billion in 2015, representing a year-over-year decrease of 3 percent.

Mentor Graphics Adds Support for Integrated Fan-Out (InFO) Packaging Technology at TSMC

03/14/2016  Mentor Graphics Corporation today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology.

Intel honors 27 companies with Preferred Quality Supplier and Achievement Awards

03/11/2016  Intel Corporation this week recognized 26 companies with its 2015 Preferred Quality Supplier (PQS) award, which celebrates exceptional performance and continuous pursuit of excellence.

Imec opens new 300mm cleanroom for 7nm and beyond chip scaling

03/11/2016  Nanoelectronics research center imec has today announced the opening of its new 300mm cleanroom.

GLOBALFOUNDRIES releases new 7SW SOI RF PDK featuring latest Keysight Technologies design software

03/10/2016  GLOBALFOUNDRIES today announced the availability of a new set of process design kits (PDKs) with an interoperable co-design flow to help chip designers improve design efficiency and deliver differentiated RF front-end solutions in increasingly sophisticated mobile devices.




TWITTER


WEBCASTS



Advanced Packaging: A Changing Landscape Rife with Opportunities

May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.

Sponsored By:
Trends in MEMS

May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Fan-Out Wafer Level Packaging

May 2016 (Date and time TBD) / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.

Sponsored By:
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TECHNOLOGY PAPERS



Protecting Electronics with Parylene

This whitepaper provides a comprehensive overview of parylene conformal coating, advantages of parylene, and applications for parylene to protect electronic devices. As technology continues to advance, devices will encounter rugged environments and it is vital that they are properly protected. Parylene conformal coating is one way that manufacturers are giving their devices a higher level of protection, along with increasing the overall quality of their products. Parylene conformal coating applications for Electronics include: · I/O & PCI Modules · Power Converters and Supplies · Backplanes · Other Embedded Computing applications · Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT

NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements

XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.

Adhesives for Electronic Applications

Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,

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EVENTS



SID Display Week 2016
San Francisco, CA
http://www.displayweek.org
May 22, 2016 - May 27, 2016
Design Automation Conference
Austin, TX
https://dac.com
June 05, 2016 - June 09, 2016
The ConFab
Las Vegas, NV
http://theconfab.com
June 12, 2016 - July 15, 2016
SEMICON West 2016
San Francisco, CA
http://www.semiconwest.org
July 12, 2016 - July 14, 2016

VIDEOS