On-Demand Webcasts



Enabling The Future Of Information Technology Without Moore’s Law Scaling


November 17, 2016 at 1:00 p.m. ET / Sponsored by Astronics

Moore’s Law scaling can no longer maintain the pace of progress just when we need it most. Data, logic and applications are migrating to the cloud, consumerization of data and the rise of the Internet of Things are placing new demands and they are all occurring at the same time. Difficult challenges in power, performance, latency, bandwidth density, security and cost threaten our ability to maintain the progress that has enabled the growth of information technology. Meeting these challenges will require reduction in power and cost per function by a factor of 104 over the next 15 years while improving performance and decreasing latency. Only a revolution in packaging through Complex 3D-SiP can provide a solution. This will require new tools for design and simulation, test, new packaging architectures, production processes, materials, and equipment. The difficult challenges and potential solutions will be discussed, including critical test issues.





DSA: Progress Toward Manufacturing Readiness


November 15, 2016 at 1:00 p.m. ET / Sponsored by Brewer Science

Directed self-assembly (DSA) patterning is one of the primary methods being pursued for future advanced patterning nodes. Since DSA’s initial introduction in the early 2000s, great progress has been made. However, many challenges remain for achieving manufacturing readiness. Key improvements in the areas of materials, defectivity, and process integration are still needed. This webcast will cover published progress to date, review key improvements needed, and discuss new advances in DSA technology. Results from CEA-LETI’s 300-mm lab-to-fab for validation of DSA’s manufacturing readiness will be discussed.





Heterogeneous Integration: An Emerging Trend for Next Generation Microelectronic Devices and a Tremendous Opportunity for Advanced Packaging


October 26, 2016 at 1 p.m. ET / Sponsored by Air Products

With the change in the traditional IC scaling cadence, the expansive growth of “Big data,” and the pervasive nature of computing, rises a paradigm shift in integrated circuit scaling and microelectronic devices. The pervasive nature of computing drives a need for connecting billions of people and tens of billions of devices/things via cloud computing. Such connectivity effect will generate tremendous amount of data and would require a revolutionary change in the technology infrastructures being used to transmit, store and analyze data. Heterogeneous integration through package with technologies such as system in package (SIP), on package integration (OPI) and fan-out (WLFO and PLFO) are poised to change the packaging industry and play a disruptive role in enabling next generation devices.





Is the Semiconductor Industry Ready for Industry 4.0 and the IIoT?


September 27, 2016 at 1 p.m. ET / Sponsored by Epicor

An industrial revolution is in the making, equivalent some say to the introduction of steam power at the tail end of the 18th century. Known as smart manufacturing, Industry 4.0 (after the German initiative Industrie 4.0), the industrial internet of things (IIoT), or simply the fourth industrial revolution, the movement will radically change how manufacturing is done. Industry experts will examine the potential for the semiconductor factory of the future, and discuss potential roadblocks.





What You Need to Know About Semiconductor Industry Greenhouse Gas Emissions


September 22, 2016 at 1:00 p.m. ET / Sponsored by Edwards

The semiconductor industry’s response to perfluorinated compounds PFCs started in 1994 when DuPont, the supplier of the primary gas used in CVD chamber cleans, C2F6, issued a sales policy restricting sales after 12/31/96 “…only to those applications that contain and either recover or destroy” C2F6 subsequent to use. The sales policy started an industry effort to understand potential impacts of all fluorinated greenhouse gases used in semiconductor manufacturing and to develop methods to estimate and reduce emissions. The industry has worked on a global basis via the World Semiconductor Council to develop common PFC metrics, measurement methodologies and approaches to reduce emissions. Preferring a pollution prevention approach, the industry and its suppliers have evaluated and implemented when feasible process optimization, gas substitution, capture/recycle and abatement. The WSC also set a goal to reduce absolute PFC emissions by 10% from baseline levels by 2010. The WSC exceeded the 2010 goal, achieving a 32% reduction, largely by replacing carbon based PFC chamber cleaning gases with NF3 in new process equipment, optimizing processes to reduce gas consumption, and using alternative chemistries and installing abatement where feasible. The new WSC2020 target calls for the implementation of best practices to further reduce normalized emissions in 2020 by 30% from the 2010 aggregated baseline. How do the semiconductor industry’s greenhouse gas emissions compare to other sectors, what data uncertainties exist, and what can be done to cost effectively achieve further emissions reductions?




Technology and Design Architectures and Process Innovations for 7 and 5nm BEOL Interconnects


September 14, 2016 at 1 p.m. ET/ Sponsored by Air Products

For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/low cost integration schemes. This webcast will discuss the key BEOL elements and innovations in these areas for the 7nm nodes and beyond. The individual elements are often in conflict with each other, but must be considered in unison to determine the overall best definition.





Flawless Execution at Fairchild: How Change to Modern MES Enables Agility, Quality and Productivity


August 9, 2016 at 1 PM ET / Sponsored by Siemens

In this high-pressure environment, leading semiconductor companies are swapping out older manufacturing executions systems (MES) for modern MES. Surprised? True, the perceived risk of changing out MES in a semiconductor facility is high. Yet companies have done it with great success and enormous business benefits. Fairchild Semiconductor’s positive experiences as it strives for quality, on-time delivery, new product introduction success, improved productivity and quality are indicative. In just one year, Fairchild switched out aging systems for a new MES at a plant in China – and the following month, they got it up at a second plant. Learn what they did to ensure the change happened quickly and without a hitch. In addition to this case study, you’ll hear from a leading industry analyst who has interviewed dozens of people from semiconductor companies that have succeeded with the move to modern MES.





Airborne Molecular Contamination Monitoring – Efficient Troubleshooting Techniques


July 28, 2016 at 10 AM MT / Sponsored by Particle Measuring Systems, Inc.

Decreasing the time to detect, contain and mitigate very low levels of Airborne Molecular Contamination (AMC) is critical for high tech manufacturers. Costs associated with AMC-related quality issues and yield losses are well understood, and adequate reduction of AMC is critical for clean manufacturers to stay competitive. Technical personnel need the flexibility to efficiently collect AMC data with good temporal-spatial resolution anywhere in the clean environment for both sustaining sample plans, as well as to collect site-specific data to converge on AMC sources during troubleshooting events. A brief overview of AMC will be presented along with the latest technology for efficiently identifying AMC sources in the cleanroom.





Fan-Out Wafer Level Packaging


May 26, 2016 at 1 PM ET / Sponsored by Zeta Instruments

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.





MEMS: Current Status and Future Directions


May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment

In 2015, the MEMS market did not grow as much as we initially expected. In the past, the Smart Phone industry was a strong driver of the MEMS industry with ever increasing volume. Today, MEMS are becoming commodity products with very low price. The webcast will review the latest market data and forecasts for the future. The MEMS “commoditization” paradox will be discussed as well as latest technical trends (sensors combos, packaging).





Advanced Packaging: A Changing Landscape Rife with Opportunities


May 10, 2016 at 1 PM ET / Sponsored by Brewer Science

Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.





Metrology Challenges and Opportunities


Thursday, April 14, 2016 at 1:00 p.m. ET / Sponsored by Park Systems

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and characterization. As the industry continues to explore new patterning methods, new phenomena further challenge metrology and characterization including pitch walking, stress relaxation in multilayer fins, and new device designs. New materials continue to be explored for transistor and interconnect applications. Here, the challenges facing materials characterization highlight the issues that will face in-line metrology when these materials transition to manufacturing.







IoT Device Trends and Challenges


January 19, 2016 at 1 p.m. ET

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.





3D NAND Challenges and Opportunities


December 16, 2015 at 12:00 p.m. ET

Flash memory has revolutionized the world of solid-state data storage, mainly because of the advent of NAND technology. However, from the technical point of view, this requires a major change in how these memories are being fabricated. This presentation will discuss this (r)evolution as well as its major scaling limitations.





System Scaling and Integration Platforms for Mobile Devices and IoT


September 9, 2015 at 8:00 p.m. ET

In this presentation, recent developments in interconnects and packaging technologies that will enable mobile devices, and IoT will be discussed. Some of these packaging technologies include high density fan-out wafer level packaging, passive and active interposers, high throughput chip-on-wafer bonding, as well as wafer level chip scale packaging for MEMS and sensors.




Lock-in Thermography for Advanced Assembly Qualification


August 26, 2015 at 1:00 p.m. ET

Increasing IoT business opportunities drive a need for new packaging techniques such as FOWLP, Embedded Component Packaging, etc. Such new assembly techniques allow more components and functionality to be integrated into an ever decreasing package space. In parallel the faster product cycle drives the need for faster production ramp to stay competitive. All these challenges highlight the need for a better methodology to determine root cause of assembly-related defects during the new package process qualification process. We will demonstrate a totally non-destructive fault localization method based on a lock-in thermography with examples in these areas.




The Path to Future Interconnects


August 6, 2015 at 1:00 p.m. ET

Jon Candelaria, Semiconductor Research Corp.’s director of interconnect and packaging sciences, will summarize a SEMICON West Semiconductor Technology Symposium Session focused on interconnects. He’ll describe the challenges for interconnect technology up to the end of the CMOS roadmap, and a few of the alternatives to address them. Next, he’ll discuss possible directions beyond the roadmap, as well as interconnectivity requirements and solution paths for emerging applications.





Isolating Electrical Faults in Advanced IC Devices


July 29, 2015 at 2:00 p.m. ET

Yield improvement and production engineers working on today's ICs encounter many challenges as defects affecting device operation go undetected by traditional in-line techniques. Electrical Failure Analysis (EFA) is a suite of techniques that helps the modern day fab increase yields by isolating faults to areas small enough for Physical Failure Analysis (PFA). In this Webinar, we showcase a few of the proven EFA fault isolation techniques and describe how EFA helps to characterize the underlying defects.





Maximize Lean Strategies with Mobile Technologies on the Plant Floor and Beyond


June 18, 2015 at 2:00 p.m. ET

With the rise of the mobile workforce, mobility is truly an ideal ‘lean’ enabler. In this session we will examine the top 10 areas where mobility can have the most impact on the success of your lean initiatives. Mobility is capable of stripping wasted time and errors out of virtually any process in any and all of your business functions, making mobility the ultimate platform to take your manufacturing operations to the next level of lean. Join us for this discussion on the factors to maximize lean strategies with mobile technologies.




Sensor Fusion and the Role of MEMS in IoT


Thursday May 28, 2015 at 1:00 p.m. EST

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.





Trends in Materials: The Smartphone Driver


Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.





3D Integration: The Most Effective Path for Future IC Scaling


Thursday, April 23, 2015 at 12:00 p.m. EST

It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.