On-Demand Webcasts

System Scaling and Integration Platforms for Mobile Devices and IoT

September 9, 2015 at 8:00 p.m. ET

In this presentation, recent developments in interconnects and packaging technologies that will enable mobile devices, and IoT will be discussed. Some of these packaging technologies include high density fan-out wafer level packaging, passive and active interposers, high throughput chip-on-wafer bonding, as well as wafer level chip scale packaging for MEMS and sensors.

Lock-in Thermography for Advanced Assembly Qualification

August 26, 2015 at 1:00 p.m. ET

Increasing IoT business opportunities drive a need for new packaging techniques such as FOWLP, Embedded Component Packaging, etc. Such new assembly techniques allow more components and functionality to be integrated into an ever decreasing package space. In parallel the faster product cycle drives the need for faster production ramp to stay competitive. All these challenges highlight the need for a better methodology to determine root cause of assembly-related defects during the new package process qualification process. We will demonstrate a totally non-destructive fault localization method based on a lock-in thermography with examples in these areas.

The Path to Future Interconnects

August 6, 2015 at 1:00 p.m. ET

Jon Candelaria, Semiconductor Research Corp.’s director of interconnect and packaging sciences, will summarize a SEMICON West Semiconductor Technology Symposium Session focused on interconnects. He’ll describe the challenges for interconnect technology up to the end of the CMOS roadmap, and a few of the alternatives to address them. Next, he’ll discuss possible directions beyond the roadmap, as well as interconnectivity requirements and solution paths for emerging applications.

Isolating Electrical Faults in Advanced IC Devices

July 29, 2015 at 2:00 p.m. ET

Yield improvement and production engineers working on today's ICs encounter many challenges as defects affecting device operation go undetected by traditional in-line techniques. Electrical Failure Analysis (EFA) is a suite of techniques that helps the modern day fab increase yields by isolating faults to areas small enough for Physical Failure Analysis (PFA). In this Webinar, we showcase a few of the proven EFA fault isolation techniques and describe how EFA helps to characterize the underlying defects.

Maximize Lean Strategies with Mobile Technologies on the Plant Floor and Beyond

June 18, 2015 at 2:00 p.m. ET

With the rise of the mobile workforce, mobility is truly an ideal ‘lean’ enabler. In this session we will examine the top 10 areas where mobility can have the most impact on the success of your lean initiatives. Mobility is capable of stripping wasted time and errors out of virtually any process in any and all of your business functions, making mobility the ultimate platform to take your manufacturing operations to the next level of lean. Join us for this discussion on the factors to maximize lean strategies with mobile technologies.

Sensor Fusion and the Role of MEMS in IoT

Thursday May 28, 2015 at 1:00 p.m. EST

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Trends in Materials: The Smartphone Driver

Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.

3D Integration: The Most Effective Path for Future IC Scaling

Thursday, April 23, 2015 at 12:00 p.m. EST

It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.

How the IoT is Driving Semiconductor Technology

January 22, 2015 at 1 p.m. EST

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will be rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.

Trends in Semiconductor Materials

Thursday, November 20, 2014 at 1 p.m. EST

The electronics industry is facing a growing crisis in being able to continue providing cost-effective processes and designs to support the continuation of what’s been referred to as ‘Moore’s Law.’ This ‘Law’, or more accurately ‘observation of the economics involved in scaling integrated circuits,' has been a very useful guideline for several decades, but as with any similar types of projections, has been expected to some day run its course. While the exact timeframe is still uncertain, that ‘day’ is now within sight, and yet there are still no clear paths forward beyond that point. This presentation will provide a brief glimpse of some of the key materials-related challenges that exist within the frontend (devices), lithography, and backend-of-line (chip level interconnects). It will also include just a few of the research concepts that offer some potential paths forward, which the Semiconductor Research Corporation and its member companies are exploring alongside the university researchers they are supporting.

Metrology and Failure Analysis

Wednesday, November 12, 2014 at 12 p.m. EST

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.