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Monthly Archives: January 2014

High cost per wafer, long design cycles may delay 20nm and beyond

Handel Jones, founder and CEO of International Business Strategies (IBS), spoke at SEMI’s Industry Strategy Symposium last week, focusing on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles. Overall, he said he believed semiconductor market growth this year will be slightly better than 2013, due in part to the strength of the global GDP.

Perhaps most surprisingly, he had a fair amount of uncertainly about 20nm.  “Will 20nm be a high tech technology node and when will that occur?” he said. “We’re tracking design starts and design completions and we see a few 20nm designs but not a lot. Frankly, whether 20nm will be big or not will really depend on two customers: one is Qualcomm and the other is Apple.” Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

Similarly, Handel believes there will be a postponement of 16/14nm. “We expect initial production in late 2016, beginning of 2017. That’s for the SoC business. The FPGA markets will be different,” he said. “There will also be delays in 10nm. Delays mean you can’t really go on the 2 year cycle or even the 3 year. I know people will vehemently disagree with that, but if you look at what’s really happening from a design start point of view and also the end customers, I think you’ll agree with our conclusion,” he said.

“If you look at the reality of the industry, 28nm high-k metal gate went into high volume production toward the end of 2013,” said, adding that they define high volume as 10% of the output. “It took almost 4 years for 28nm high-k metal gate to go into high volume production. Now we’re basically starting 20nm. Even if the fabs are ready what you have is the design cycle time. Preparing libraries and IP can take six months at least. Doing a complex design in 20nm can take you at least a year. Validating the design can take you another half a year. If it’s a modem, and you need approval from the carriers, that’s another half a year. Even if the fab is ready, you start these things and it’s two years,” he said. “We have an industry that is trying to adopt three technologies in three years. It’s impossible,” he said. “It’s not realistic from an infrastructure point of view, even if it the fabs are there, for three technology nodes to ramp in three years.”



Handel said that application processor (AP)/modem design can cost about $450-500 million in 16/14nm, with a timeframe of around 18 months. “You need 10X revenue so for that design, so if you’re spending $450 million, you need $4.5 billion in revenue. A few companies can get that, but not many,” he added.

“The economics of the industry are forcing changes. You’ve seen them already. The long ramp up time for 28nm HKMG, and 20nm with double patterning is clearly a major challenge from a technology point of view, and a bigger challenge from a cost point of view. FinFETs will be an even bigger challenge. Intel is having delays in their 14nm FinFETs, whether in high volume at 22nm, how will companies that have never done FinFETS before, how will design companies that have never designed in FinFETs before, how will they ramp faster?” he asked.

 Not surprisingly, Handel also had a dim outlook for 10nm. He estimates that 10,000 wafers/month at 10nm will cost more than $2billion. “If you want to install 40,000 wafers/month, it’s going to be an $8 billion bill. If you want to install 100,000 wafers/month, it’s going to be $20 billion. Even before you get to 450mm, it’s going to be significantly more capital intensive,” he said.

Just looking at the location of the headquarters of semiconductor companies, he said the U.S. was still strong, but there was also strong growth from Korea – mostly in the form of Samsung – but also China and Taiwan. “We see a relatively flat Europe and then a continuing decline in Japan. In fact, we don’t see Japan strengthening unless we see some major changes,” he said.



That also has an impact in terms of the technology requirements. In terms of minimal dimensions, Handel most of the advanced technology designs are in the U.S., with advanced technology defined as being 28, 20 and now starting 16/14nm. “In developing countries, many of the designs are still at 40nm. 28 is a new technology and the next technology after 28 is going from polysilicon up to high-k metal gate,” he said.



Handel also sees uncertainly in the use of FinFET devices due to higher wafer cost. “We see quite a few new designs. The problem again is the cost per wafer. For 28nm, we have about $2600 and for 20nm we have about $3200 and for 16/14 we have about $4000. You now have this increasing cost per wafer and can you get the higher gate density and can you also get higher parametric yields?” he asked.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”

The magic behind the gadget and the need for innovation

Rick Wallace, president and CEO of KLA-Tencor, provided the keynote talk at the SEMI Industry Strategy Symposium (ISS) this year, held Jan 12-15 in Half Moon Bay, CA. He said he believes the semiconductor industry might be facing a “Concorde” moment, referring to the demise of supersonic passenger transport, the last flight of which was on 24 October 2003. “That failed not because of technology but because of economics,” Wallace said. He sees a similar challenge coming down the road for continued scaling. “Moore’s Law is much more likely to die in the boardroom than the laboratory,” said.

Wallace also spoke about “The Road Less Traveled,” seeming to indicate that the more traveled one is that of consolidation, which Wallace said leads to “losses in agility, flexibility and innovation.” He said larger firms are not effective at driving innovation although they are effective at driving continuous improvement. “It’s tough to see how a large scale merger makes a company better,” he said. “Some firms will be too big to fail but my fear is that they will become too big to innovate.”

The solution he said is young people. “We need to attract the young talent if we want real innovation. The longer you’re around the more you see what can’t be done,” he said.

Wallace told a story about explaining to his 10 year old daughter what his company by using the iPad as an example. His daughter thought about it and said she understood: it was the magic behind the gadget.

Part of attracting young people to the semiconductor industry is through education. After Rick’s presentation, Denny McGuirk, president of SEMI, presented an award to Rick and to L.T. Guttadauro, president of the Fab Owners Association, in recognition of their work on SEMI’s High Tech University (HTU). HTU is a career exploration program that encourages student interest in science, technology, engineering and match. Since 2001, the SEMI Foundation has delivered 143 programs to 4800 students and teachers worldwide.

Although some view the semiconductors as a commodity, hopefully efforts such as that of the HTU will explain the magic behind the gadget. “Who doesn’t want to work on magic?” Wallace asked.

50 years ago: January 1964

The origin of Solid State Technology began in 1958, the same year that Jack Kilby of Texas Instruments invented the integrated circuit (the invention of the transistor is credited to Bell Labs; the first transistor was demonstrated on December 23, 1947). The initial name of the magazine was “Semiconductor Products” and that was changed to “Semiconductor Products and Solid State Technology” by 1962.  

In this news series, we’ll look back 50 years and see how much has changed.. or perhaps more often, how much hasn’t.  

In January of 1964, it was clear that microelectronics were here to stay, and were rapidly changing the shape of the electronics industry (Gordon Moore did not propose his now famous Moore’s Law until April of 1965, more than a year later. Intel was not founded until 1968). In the Editorial in the January 1964 issue, Editor Sam Marshall writes that estimates for the market for microelectronics in 1964 “vary between 25 and 50 million dollars.” The market exceeded $300 billion in 2013.002 (444x640)

Sams adds: “There is a parallelism between the manner in which semiconductor devices have gradually displaced vacuum tubes, and the manner in which microelectronics is encroaching into the territory formerly enjoyed by discrete devices such as diodes and transistors. This movement is directly related to the increasing demands for higher frequencies of operation, greater miniaturization and surprisingly enough, reliability.”

Sam also foresaw how the relationship between design and manufacturing was getting more complex and even hints at the trends toward the fabless/foundry model. He said that a new order of procedure must be followed.  “The engineer must either turn over his proprietary design to a firm engaged in microelectronics manufacturing or he might search the open market for functional blocks that will best meet his needs. In either case, an unhealthy situation arises. In the first case, the design engineer has to reveal information which could jeopardize his firm’s market advantage. In the second case, the manufacturer who merely purchases functional blocks and assembles them into a product justifiably feels that he has lost his status as that of a true manufacturer and has become nothing more than an assembler and tester.”

The issue had a feature on electron beam processing of semiconductor devices, which noted how useful the analysis of X-rays generated from e-beams could be for metrology. “The technique is extremely useful in determining which elements are present on the specimen surface as well as detecting local variations in their concentrations after such treatments as localized melting, annealing, diffusion and oxidation.” Today, energy dispersive x-ray spectroscopy or (commonly called EDS, EDX or EDAX) is widely used.

Perhaps the most obvious change in the last 50 years: wafer size. Note these two advertisements, one touting a production breakthrough of 40mm wafers (that’s a little over 1.5 inches), the other depicting a wafering machine. Of course, today the industry is working with 300mm wafers and contemplating going to 450mm. It’s also interesting to note the die size, number of die per wafer and pincount shown on the left, although it’s hard to say if that was typical of the time.

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Other odds and ends from 1964: Kulicke and Soffa reported its sales fro the fiscal year ending Sept 30, 1063, were $3,615,519, an increase of 95%. ITT planned to construct a 135,00 square foot, $3 million plant in West Palm Beach, FL to manufacture integrated circuits and other semiconductor devices. Philco Corp.’s Lansdale Division (which produced Indium Antimonide IR detectors among other types of electronics), planned to triple the divisions facilities for microelectronic engineering and product development, with plans to develop new production facilities capable of producing 10,000 silicon microcircuits per month by Spring of 1964. Total 1964 R&D expenditures in the U.S. were expected to reach the $20 billion mark. In 1963, about $18.3 billion has been spent on R&D compared to $16.6 billion in 1962. Advanced achieved with graphite and carbon as engineering materials were detailed by Speer Carbon Co.  A novel approach to the fabrication of a high speed tunnel diode was described by IBM: a gallium arsenide, planar, epitaxial device. Today, the potential of tunnel transistors is being discussed as a replacement to FETs. Based in part on what? Gallium Arsenide! The more things change…

Coming next month: GaAs IR emitters, tunnel diode amplifers and thermal resistance of transistors.