Insights From Leading Edge

Monthly Archives: February 2012

IFTLE 90 Highlights from the IEEE 3DIC 2012 Japan

The 2011 IEEE 3DIC Conference scheduled for Japan, as most of you know, was postponed due to the earthquake and Tsunami issues Japan experienced last year. The good news is that the conference which was postponed till Feb 2012 was held a few weeks ago and was a huge success. More than 250 attendees shared 32 presentations and more than 65 posters concerning the latest breakthroughs in 3D stacking technology.

In the next two blogs we will review what IFTLE considers some of the more important presentations and posters.

Effect of Sidewall Roughness on Leakage Current

Fujitsu has looked at the effect of sidewall roughness on leakage current comparing Bosch etched TSV to ULVAC NLD etched TSV (discussed below). Bosch etched scallops were 72 nm deep and 280 nm long while the NLD etched TSV were ultra smooth. 500 nm of SiON insulator was deposited by low temp PECVD (150C) followed by PVD of 50 nm of TiN and 50 nm of TI to serve as Cu barriers followed by 200 nm of Cu seed.

Leakage current between TSV was measured after annealing for 5 min at from 200 to 400C. Leakage current of NLD is lower than the bosch etched TSV initially and is less than 100x smaller than Bosch after anneal at 400C. These results are correlated with cracking of the insulation layer and subsequent migration of copper. It appears as though sidewall roughness initiates crack growth. Since anneal at 400+ is recommended to reduce the effects of copper protrusion [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC…"], it is recommended by IFTLE that such leakage current experiments be run when optimizing Cu anneal process during TSV fabrication to insure integrity of the barrier and insulation layers after processing.

(Click on any of the images below to enlarge them.)
Effect of Sidewall Roughness on Copper migration

Koyanagi and his co-workers examined the influence of copper contamination on device reliability and found that when Bosch scalloping is high, conformal deposition of the dielectric layer and barrier layer is difficult and increases the likelihood of Cu atom diffusion through the thinned barrier on the point of the scallop especially during the thermal temperatures reached during post process thermal anneal.

They fabricated Si trenches with 5 um diameter and 10 um depth with sidewall scalloping of 30 and 200 nm. 100 nm thick oxide and Ta barriers of 10 or 100 nm where deposited by sputtering. This was followed by a 200 nm thick copper seed.

Electrical results showed the 10 nm Ta barrier failed to resist Cu migraion for both the shallow and severe scallops.

ULVAC non Bosch scallop free TSV

The magnetic loop discharge plasma (NLD plasma) used by ULVAC can be used for silicon or oxide etching. The etch profile is controlled by the SF6/O2 ratio. Sidewall roughness of less than 15 nm is obtained.

IMEC and Suss Demonstrate Integration of ZoneBond Process

IMEC has demonstrated integration of the ZoneBond process on their Suss XBC300-LF temporary bond cluster and DB12T peel debonder. The Zone bond process has been described before [see IFTLE 61, "Suss 3D Workshop at Semicon West"]

The bonding material is coated on the wafers in 19.2 +/- 0.4 um thickness. Scanning acoustic microscopy shows that the bonding to a silicon carrier is void free.

After thinning and backside processing the bonded wafers are soaked for a few hours in the adhesive solvent and laminated onto a UV sensitive dicing tape. The carrier wafer is then "peeled" off the device wafer.

The remaining glue is then removed while the device wafer is held on the film frame. Devices are diced subsequent to cleaning.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………………

IFTLE 89 Advances in CMOS Image Sensing

It was 5 years ago in the the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS) [see "PFTLE 12 Imaging Chips with TSV announced…"; PFTLE 16, "More TSV Commercial capacity on line"; PFTLE 24, "ST Micro announces more CMOS Image Sensor Packaging Capacity with TSV"; PFTLE 57 "Toshiba CIS Camera Module Details…"; etc]. The next step of circuit repartitioning and stacking was interrupted by "back side imaging" [BSI], which flipped the chip over and let the light enter through the least obstructed side to let more light in per pixel, which is really important as the pixels are getting smaller and smaller. [see PFTLE 40, "Backside Illumination next for Next Generation CMOS Image Sensors"; PFTLE 46, "on Mechanical Bulls, Rollercoasters and CIS with TSV."

For those of you needing a refresher about how this is done, below is a process flow that Yole Developpment released in 2010 starting with SOI wafers.

(Click on any of the images to enlarge them)

From SOI to Bulk Silicon

Last spring Chipworks announced that Sony had moved from an SOI based process to a bulk silicon process. [link] It is unclear yet whether this will become an industry wide trend.

Chipworks found that while previous Sony BSI sensors they had analysed were fabricated using an SOI starting wafer, with the 1.1µm BSI generation, Sony migrated to using bulk silicon substrates instead of SOI. Chipworks commented that SOI is a more costly substrate, but likely an easier process to implement. They presume that Sony was able to identify the yield limiting contributions from the bulk polishing process, and fine tune the yield to achieve a high yielding and very cost effective process. This process would require a SiO2 bonding process.

In late August Ziptronix announced that Sony had taken a license on Ziptronix’s patents regarding oxide bonding technology for backside illumination imaging sensors [see IFTLE 65, "…Ziptronix Licensing News"]

With BSI fully implemented, it appears that practitioners have now turned their sites back to repartitioning the circuitry and creating true stacked 3D IS structures.

Sony reveals stacking in BSI CMOS Image Sensor

In January Sony announced that it had developed "the next generation back-illuminated CMOS image sensors" by separating the pixel section containing the back-illuminated structure pixels from chips containing the circuit section for signal processing, which is in place of supporting substrates for conventional back-illuminated CMOS image sensors. [link] This results in:
-More compact image sensor chip size
-Higher image quality of the pixel section by optimizing the manufacturing processes for superior image quality on the pixel layer
-Faster speeds and lower power consumption by adopting the leading edge processes for the circuit section

By this stacked structure, large-scale circuits can now be mounted keeping small chip size. Furthermore, as the pixel section and circuit section are formed as independent chips, a manufacturing process can be adopted, enabling the pixel section to be specialized for higher image quality while the circuit section can be specialized for higher functionality, thus simultaneously achieving higher image quality, superior functionality and a more compact size. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits. Basically some of the attributes that we have been ranting about for 3DIC for the past 5 years. Samples will be shipped starting in March, 2012.

Poly SI TSV found in the Toshiba BSI CIS from Fujifilm Camera

Chipworks reverse engineering analysis of the Toshiba HEW4 BSI TCM5103PL 16 Mp, 1.4um Pixel Pitch CIS found inside Fujufilm F550 EXR camera. The CIS was fabricated using the Toshiba Oita 300 mm wafer line, using a 65 nm logic process adapted to BSI image sensor production. Fellow SST blogger Dick James [link] was kind enough to share more of the details for our IFTLE readers.

With BSI, the I/O pads end up on the bottom side of the sensor silicon (which is bonded to a handle wafer so the pads are burried). To get to the pads, you need some means of creating a via through the silicon to the front side metal. Very high density arrays of polysilicon filled through silicon vias (TSVs), to form the electrical interconnect between the back side aluminum bond pads and the front side copper lines on the CMOS integrated circuits. These are the first true submicron TSVs that Chipworks has seen deployed in volume production.

Chipworks notes that: "…closely packed, poly-filled submicron TSV… technology is non-trivial to implement. Once mastered and with appropriate economies of scale in play, however, this advanced TSV process saves valuable silicon area and can reduce the size of the camera module."

Applied Materials Targets BSI Sensors Manufacturing

Applied Materials recently announced the Applied Producer Optiva CVD system aimed at the manufacture of BSI sensors. "Emerging BSI image sensor designs present a new opportunity for Applied Materials to provide customers with the technology they need to be successful in this rapidly growing market"

The Optiva low temperature process runs on their Producer platform, capable of depositing low temperature, conformal films that boost the low-light performance of the sensor while improving its durability. The system enhances the performance of the microlens by covering it with a tough, thin, transparent film layer that reduces reflections and scratches, and protects it from the environment. Importantly, the Optiva tool is the first CVD system to enable 95% conformal deposition at temperatures less than 200C. As typical bonding adhesives have thermal budgets of approximately 200C, all subsequent processing on these temporarily bonded wafers must be done below 200C.

iSuppli estimates that 75% of all smartphones will be fitted with BSI sensors in 2014, up from just 14% in 2010. 2014 demand is estimated at 300 million units.

Coming up in IFTLE:
– Advanced packaging highlights from NEPCON Japan
– 3D highlights from the IEEE 3DIC Conference in Japan

For all the latest in 3D IC integration and advanced packaging stay linked to IFTLE……..

Hope to see you all at the IMAPS Device Packaging Conference in Arizona next month!
IFTLE will be hosting a session on 2.5/3D Infrastructure development.

IFTLE 88 Apple TSV Interposer rumors; Betting the Ranch ; TSV for Sony PS-4; Top Chip Fabricators in Last 25 Years

Apple about to Join the 2.5D TSV club?

Click on any of the images to enlarge.

It’s not news that Apple has been considering moving fabrication of its A6 ARM processor from its current supplier Samsung to TSMC. The "A6," was scheduled to appear in the iPad 3 later in 2012. [link]

By mid 2011 there were many reports that TSMC had started tooling up its 28 nm process to fabricate the A6 for Apple. The Apple A6 will be based on an ARM Quad Core Processor.

Mid summer rumors were that the A6 would use "Intel 3D technology" technology , but recall this was the period in which several publications were totally confused over the difference between a finFET and a 3DIC [ see IFTLE 62, "3D and Interposers – Nomenclature Confusion…"] so I wasn’t really sure what they meant.

More recently statements like "The A6 is reportedly being built on TSMC’s new 28nm process and incorporates the company’s 3D chip-stacking technology. The use of through-silicon-vias (TSVs) and chip stacking could significantly improve the A6’s power consumption compared to conventional planar silicon, but it adds a layer of complexity that could benefit from additional ramp time" make it much clearer that Apple is truly looking for 3D IC technology for their next generation products.[link]

In fact EE Times has just reported that TSMC has had to do a "respin" on their A6 processor design and that "one potential reason of the respin is that TSMC plans to use 3-D stacking technologies along with its 28-nm manufacturing process in the production of the A6 for Apple. The use of a specialized silicon interposer and bump-on-trace interconnect may produce specific requirements in the main processor die." [link]

Thus IFTLE now finds that it is highly likely that 2012 will bring us at least announcements (if not actual production) from Apple that their next processor will make use of 3D IC technology.

How many IC Fabs are Ready to "Bet the Ranch"

Growing up as part of the first TV generation in the USA (my family got its first TV in 1954 when I was in kindergarten), many psychologists have said that the impact of TV on my generation was profound. After Howdy Doody (a puppet show) and Crusader Rabbit (the first animated TV show by the group that later brought us the cult classic Rocky & Bullwinkle) my favorites shows were the westerns like "Have Gun will Travel" and "Rawhide" (which gave us Clint Eastwood). Part of all great westerns is the poker game in the saloon. The "good guy" (always in the white hat) is always the underdog and the "bad guy" (in the black hat) always has a table full of chips. When the good guy finally gets a hand that cannot be beat, the bad guy always bets more chips than the good guy has left on the table. That’s when the good guy literally "bets the ranch (or maybe the farm)" on his unbeatable hand. Why he happened to be carrying the deed to his property in his back pocket was never actually explained. That phrase, "betting the ranch" has survived into today’s lexicon and that’s what a lot of microelectronic companies will be asked to do if they want to move forward with advanced technologies.

IC Insights recently reported that Intel and Samsung plan $12.5 billion, $12.2 billion in capex respectively which is more than double the 2012 capex of TSMC (budgeted $6.0 billion). Combined, Intel, Samsung, and TSMC are forecast to account for about half of the total semiconductor capex spending in 2012.

Samsung currently serves as Apple’s foundry partner for the A4 and A5 application processors used in iPad tablet computers, iPhones, and iPod touch devices. Besides serving as a foundry partner for Apple, Samsung is aggressively ramping its in-house application processor business as demand increases for its smartphones, tablet PCs, and other mobile/media related devices. Meanwhile, the remaining $5.7 billion of Samsung’s capex budget will be applied to the production of memory ICs, with a good portion of the funding likely to be used to boost capacity for NAND flash memory.

Intel is nearing completion of, and will soon be equipping and ramping production at, three new wafer fabs located in Chandler, AZ, Hillsboro, OR, and in Ireland. The company plans to begin 14nm production in Chandler when that fab opens in 2013. The new Hillsboro facility will focus on process development using 450mm wafers when it begins operations in 2013. Meanwhile, several fabs will begin 22nm production in the second half of 2012.

Samsung, Intel, and TSMC are positioning themselves as the strongest and most dominant IC suppliers in the industry and if anyone want to challenge that — well they may have to bet the ranch! Weaker suppliers will be forced out of the business and a higher percentage of capex spending will be in the hands of the fewer remaining players.

Sony says it wants TSV packaging for updated Playstation 3

Masaaki Tsuruta, CTO of Sony Computer Entertainment, says that the company is working on a system-on-chip (SoC) for their fourth generation console which will not be called PlayStation 4. [link] The engine that powered the PS3 reportedly cost $400MM to develop; the main SoC for the new console could be the first $1bn hardware design project.

Tsuruta indicated that there is likely to be a 3D stack incorporating TSV technology in the next generation console. Sony’s target of no more than 50ms latency even for 8k x 4k resolution at 300fps, clearly points to the need for a highly integrated TSV-based package although Tsuruta warns "We will have to work with a lot of third-party partners to make these things happen."

Noting the recent difficulties that several fabs are having trying to achieve viable yields at 28nm, Tsuruta commented that he believes that these problems are now moving towards a resolution.

Semiconductor Leaders Over the Last 25+ Years

Our friends over at IC Insights recently put together a Look at the Semiconductor Industries top 10 sales leaders over the past 25+ years. In case you haven’t seen this, I thought you might like to take a look. You can interpret these results without any help from me.

For all the latest on 3D IC and advanced packaging stay linked to IFTLE……………………