This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. We’ll first take a look at some of those and then look at several key presentations from the conference.
Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.
Handset thickness continues to be reduced and is now approaching 6mm. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Most of these packages are FC and WLP. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC.
Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant. Warpage is dependent on :
– core thickness, CTE and modulus
– EMC thickness over die
– die thickness (ratio of Si/EMC).
Solder balls have become a significant fraction of the total package height.
Tighter pitch requirements ( < 140um) have necessitated a move to copper pillar connections which in turn need thermocompression bonding to overcome warpage/flatness issues in such structures.
Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus.
Bezuk reports that typical HVM substrate properties in 2014 are as follows:
Current 2014 HVM
Patterning Method (µm)
Min FC pitch (µm)
Core material CTYE (ppm)
Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus.
Bezuk proposed that the next move (time undefined) will be from today’s FC PoP structures to 2.5/3D moving first to wide IO DRAM on logic and next to logic-on-logic. Although he added that there was no clear infrastructure answer for where interposers will be coming from.
Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below.
Despite all the talk about high density laminate technology approaching < 5um L/S, Prior indicated that the Apple 5S was the first device to use 50um L/S and CSPs on a 0.4mm pitch. It is also interesting that caps continue to shrink. 01005 is 0.4 x 0.2 x 0.13mm which is extremely hard to assemble.
The Apple A7 processor is packages in PoP with the memory package being 1Gb of LPDDR3. The substrate has 27um L/S and 150/170um bump pitch. Memory chips are Ag WB which is a lower force assembly process than Cu WB. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018.
Prior showed the following application processor roadmap for phone/tablet low end vs high end products.
Transition to 0.4mm packages
FBGA and WLP are in high volume production at 0,4 and 0.35mm pitch. Wafer CSP moving to 0.3mm and below. Prismark forecasts > 28% of CSP/WLCSP to be 0.4mm or less by 2018.
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