Insights From Leading Edge

Monthly Archives: March 2017

IFTLE 328 IMAPS DPC Part 1: New MIL Qualified Player in FOWLP

By Dr. Phil Garrou, Contributing Editor

The annual IMAPS Device Packaging Workshop was held at its usual location outside Scottsdale AZ in early March. I noticed at this years meeting among the > 600 attendees were lots of new young faces who had no clue where this meeting came from.

Keeping the Historical Record Straight on IMAPS DPC

AndySince IFTLE is very picky when it comes to keeping the historical record straight, I just wanted to take a few seconds to remind the readership that this meeting was the brain child of Dr. Andy Strandjord who was both a colleague, in our days developing BCB at Dow Chemical, and the Tech VP of IMAPS at the time. In the early 2000’s there were several IMAPS workshops taking place on related thin film packaging topics like MCMs (now called system in package, SiP), bumping and the newly developed wafer level chip scale packaging (Fan in WLPs). Andy pulled them all together into tracks and initiated the Device packaging “workshop” which is really a conference complete with extensive exhibitions, but with no requirement to write a full paper for submission. The first one was held in 2005 and was an immediate success. Next to the fall IMAPS meeting that IFTLE calls the “National” this is the 2nd largest IMAPS packaging focused meeting in the US and after the national and IEEE ECTC is the 3rd largest packaging meeting in the US period. Ted Tessier followed Andy as General Chair for a few years and I was chair in 2010 and 2011. Since then, Chairs have rotated out of the technical committee. Now back to this years conference.

Aurora Semiconductor

I had heard rumors that there was a startup company doing FOWLP which was MIL qualified. Ends up this company is Aurora Semiconductor which spun out of DRAPER Labs in early 2016 by buying the St Petersburg FL facility. They indeed are DOD cleared, ITAR registered, ISO 9001 and are a DMEA Trusted Foundry Program member and accredited supplier.

IMAPS DPC was the first public presentation that I had seen from them, and is worthy of a closer look.

They have branded their technology 4DHSiP.

  • Patented and licensed MCM approach
  • Compatible with COTs (commercial off-the-shelf) components
  • Chips first technology; FOWLP (Fan Out Wafer Level Package),

Aurora 1

Similar to traditional eWLB technology chips are placed face down and overmolded into a wafer. The chips are then interconnected with RDL. These layers are then stacked and connected with through mold vias (TMV). They claim:

  • 4 total layers of interconnect (7 topside and 7 bottom)
  • Controlled Impedance Transmission lines
  • Power/Gnd Bus; Multiple Power Domains
  • Signal line Shielding for crosstalk isolation

Aurora 2

They have developed several techniques including metallic “fins” and “bridges” to conduct heat away. Thermal control appears to be a work in progress.


Santosh Kumar of Yole Developpement gave a new forecast for TSV applications as shown below. They project the market to increase to $7.2B by 2021. 3D memory stacks will grow at the highest CAGR – 48%. By 2021 MEMS & Sensors will become the biggest contributor to TSV application revenues.

Yole 1

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IFTLE 327 SEMI 3D Summit Part 3: Increased Use of Sensors; HVM FOWLP Applications

By Dr. Phil Garrou, Contributing Editor

Finishing our look at the 2017 SEMI 3D Summit in Grenoble.


Thibault Bisson of Yole discussed 3D packaging as a key enabler.

Yole predicts a significant increase in the use of sensors in smartphones. While the use of sensors was limited to 3 during the advent of the smartphone in ~2007 (microphone, accelerometer and CIS), by 2021 they expect more than 20 sensors in the advanced smartphones.

yole 1

Smartphone APU options, their packaging and specs are shown in the chart below.

yole 2

System Plus Consulting

Romain Faux of System Plus Consulting presented a “technology and cost review of 3D packages in HVM.”

Sys Plus concludes that FOWLP could lead to cost reduction under several conditions:

– In replacement of a chip on board radar chipset.

– In combination with advanced CMOS nodes for single die consumer applications such as baseband, power management, Rf transceivers and/or audio codec solutions.

– in 3D PoP configurations for thin AP + memory solutions.

An interesting comparison is between the 77GHz radar chip sets packaged on COB vs FO-WLP as shown below. One can easily see the miniaturization achieved.

Sys plus 1

Other HVM FOWLP examples include audio codec, power management ICs, Rf transceivers and Application processors.

Sys plus 2

Sys Plus projects a 10% cost savings on the audio codec and a > 50% cost savings on the Rf transceiver.

While Amkors TMV is the predominant package for Application processors, he newer technologies such as the MeCP by Shinko and he InFO by TSMC offer better integration and lower package thickness. Specifically, the TSMC InFO package shows a thickness reduction of 30% while eliminating the laminate substrate.

sys  plus 3

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IFTLE 326 2017 SEMI Euro 3D Summit: Thermo-compression Bonding and Plasma Dicing

By Dr. Phil Garrou, Contributing Editor

Continuing our IFTLE look at the 2017 SEMI Euro 3D Summit.


Alistair Attard of Besi discussed “Productivity Improvements in Thermo-compression Bonding (TCB)”.

TCB allows stacking of thin devices at ultrafine pitch ansd as such is an enabling technology for 2.5D and 3DIC stacking. Currently TCB mainly addresses low value high end applications which are performance and form factor driven and have lower cost sensitivity. TCB can be used with non conductive paste, capillary underfill or non conductive films.

Besi 1



– Not well suited for 3D integration (dispensing at each stack layer, NCP bleed, etc.)

– Challenging process for thin dice (< 50μm) due to NCP climbing to the top of the die

– Underfill flow issues for high density fine-pitch bump arrays

– Risk of NCP entrapment in the solder joints


– No issues with adhesive bleed, adhesive entrapment, thin die handling, tool contamination

– Mature CUFs are available

– Proven process for HVM of memory stacks

BUT – Longer process times due to increased process control and solder solidification

– solder joints are not protected until the underfill step – greater risk of joint cracks


– NCF solves some issues of NCP & CUF, but it is still challenging

– Ideal process for thin die & 3D applications

– Reduced die stress due to presence of NCF (good for ULK)

– Shorter process times and collective bonding strategies enable higher UPH

– NCF voiding needs to be controlled

– NCF not yet a mature process

When compared to flip chip mass reflow, TCB is ~ 2X more expensive and is at least 5X slower. In order to be used in larger applications, these issues must be improved upon.

Productivity is increased by reducing the overall TC process time by either of the two approaches shown below (being called Vertical Collective Bonding or VCB):

Besi 2

Besi claims that VCB (gang bond in press) will reduce COO > 5X.

VCB bond profile needs to be optimized (Force, Temp, Timing)

– to get good NCF flow before solder reflow

– to minimize NCF voiding

– to get good soldering at all die levels


SPTS (Orbotech)

Dave Butler of SPTS (now Orbotech) discussed “Plasma Dicing is Becoming Mainstream”.

Conventional dicing includes the following techniques:



Plasma dicing, being offered by SPTS and others uses the same plasma source as DRIE, with the following reported advantages:

No Damage

– Clean, chemically etched scallops

– Active cooling to prevent wafer heating

– Increased die strength

– Yield improvement –no cracking or chipping with plasma dicing

– Advantage for thinner wafers (≤50μm)

Die Density

– Narrow lanes (<10μm) increase usable Si area

– Crack stop areas can be eliminated


– Parallel process

– High Si etch rates –even with more lanes for smaller die

– Option to use cluster platforms

SPTS reports plasma dicing gives ~ 2X die strength vs typical dice after grind techniques.


Reinhard Windemuth of Panasonic also presented info on “Advanced Plasma Dicing”. Pointing out the same advantages as SPTS, Panasonic reports ~ 20% increase in 0.5mm chips from an 200mm wafer due to the reduction in the size of the dicing streets as well as the near elimination of chipping and damage layers as shown below.

panasonic 1

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IFTLE 325 Omnivision takes Ziptronix License; Semi Europe 3D Summit Part 1

By Dr. Phil Garrou, Contributing Editor

Before we take a look at the recent SEMI European 3D Summit, a little news on the licensing front.

OmniVision Signs License Agreement with Ziptronix

Well, actually Ziptronix as we all know by now was acquired by Invensas, a division of Tessera, in the fall of 2015.[see IFTLE 253 “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix … “]

But now, Tessera has changed its name (as of Feb 22nd) to Xperi (link).

The key issue here is that Ziptronix owns patents for direct oxide bonding and copper/oxide so called hybrid bonding ( they call tehse technologies Zibond and DBI). This technology that is being used extensively in the CMOS image sensor (CIS) market and was licensed to Sony, the accepted world leaded in CIS in 2011 [link]

There has been ongoing litigation with Omnivision over violation of the Ziptronix patents since 2010. [link]

A few weeks ago that litigation was resolved when Tessera announced that its subsidiary Ziptronix had reached a licensing agreement with OmniVision. In turn, the outstanding litigation by Ziptronix against OmniVision and TSMC has been dismissed.[link]

FYI, the Ziptronix IP has also been licensed by aerospace leaders Raytheon, Teledyne and supplier Novati.

2017 SEMI European 3D Summit

The Annual SEMI European 3D Summit took place in late January in Grenoble France. For the next few weeks we’ll be taking a look at some of the interesting presentations that were given there.

Meyer – Infineon

Thorsten Meyer, one of the early players in FOWLP used a great simple slide to show the advantages of FOWLP over 2.5D interposers for select lower density cases. Basically the FOWLP (like eWLB) can reach the 200um pitch directly without the high cost silicon interposer. When this can generate enough IO for your application, this could be the most economical solution.

Intel 1


Wolf – Fraunhoffer Institutes

Juergen Wolf examined the technologies available in the Fraunhoffer institutes for “Heterogeneous Integration for 3D systems.”

Of interest is their work with Osram and Infineon to develop GaN LED chips n Silicon drivers as shown below.

Wolf 1


Wolf also announced that Fraunhoffer is working with Ziptronix on their DBI bonding technology and showed a 96% yield on DBI test vehicles.

  • DBI is an extension of Ziptronix’ ZiBond technology that allows an interconnect pitch of less than 10-microns, and accommodates 1.5 million connections per square centimeter.
  • The process uses advanced tools to planarize the wafer surface and allows hermetic bonding SiO2/Cu at low temperatures (300°C).
  • Technology is jointly developed by Invensas and IZM ASSID & partners

wolf 2

Also of interest was their interposer roadmap which included not only TSV but also integrated passives, embedded chips and fluid cooling channels down the road.

Gen 1 Interposer = TSV, multi layer redistribution(RDL)

Gen 2 Interposer = + integrated passive devices

Gen 3 Interposer = + embedded active devices and/or MEMS

Gen 4 Interposer = + integrated optical & electrical interconnects

Gen 5 Interposer = + active cooling (e.g. fluid channels)

Groothuis – Samtec

Steve Groothuis discussed the use of glass interposers. Samtec acquired Triton Microtech (a glass interposer startup) last year. Their approach is to use thin fil RDL with thick film filled vias. “Samtec Microelectronics will be processing borosilicate glass, fused silica, quartz, zirconia, and sapphire wafers and eventually panels for cost and scaling.”

While they acknowledge that the glass interposer platform has not become mainstream yet, they contend that glass interposers are a strong candidate to be used in RF applications because of superior electrical insulation, low dielectric constant, high hermeticity, low warping, and high resistance to corrosion. Their design rules are shown below.

samtec 1

Samtec shows copper diffusion data and concludes “No diffusion of Cu into the glass –No need for a barrier layer along sidewall,” this leaves me somewhat puzzled since the last time I checked glass was SiO2 and we now Cu diffuses like a rabbit in SiO2. Maybe the expts were not run under bias?

They conclude that Samtec will work with customers in various areas of Glass Core Technology for prototyping, low-volume production, and paths to high-volume manufacturing.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 324 Intel EMIB Implementation in the Stratix MX

By Dr. Phil Garrou, Contributing Editor

At the recent IEEE ISSCC in SF, Intel discussed the implementation of their EMIB technology [Embedded Multi-die Interconnect Bridge] technology in the Altera Stratix 10 FPGA family designed to meet the needs of developing high end communications systems.

EMIB was first proposed by Mahajan and Sane in USP 8,064,224 which was filed in 2008 and issued in 2011 [link].

A nice description of the technology was given at the 2016 ECTC [link]

EMIB uses thin pieces of silicon (< 75um) containing fine pitch interconnect (~2um L/S) embedded in an organic substrate to enable dense die to die interconnect between die on the BGA like laminate substrate as shown below.

X sect


Assembly is by a combination of 55 micron micro-bumps and 100+ micron FC bumps to support up to 24 transceiver channels with 96 I/Os each. They deliver 2 Gbits/second/pin at 1.2 pJ/bit/die using a proprietary protocol. Currently, the bridge links four 28 GHz serdes to the FPGA.

Intel has shown the following process sequence for EMIB:



Altera [now Intel’s Programmable Systems Group (PSG)] will have a family of their upcoming Stratix 10 line that will include HBM DRAM 3D stacks from SK Hynix connected to the FPGA with Intel’s proprietary EMIB technology. They report up to 10x the memory bandwidth available by connecting the FPGA to off-chip memory.

The HMB2 DRAM chips themselves are 8Gb each, and they can be stacked up to 8 high, yielding an 8GB 256GB/s lane. Combine four of these stacks for a 1TB/s aggregate memory bandwidth. Power consumption is reduced because the memory is right next to the FPGA and drive strength is much smaller.

Intel 1

The parts integrate four stacks of HBM2 DRAM, each with up to four memory dice. Each stack can run to 256Gbyte/s, so four stacks give 1Tbyte/s, and there are still transceivers and I/O available for use with external components.

memory solutions

One can conceive of application areas such as HPC (high performance computing), cloud computing and data centers. So far, Intel has announced no other users of this EMIB technology which they made available as a foundry service two years ago. It will also be interesting to watch how Intel’s EMIB competes with the other “fan-out “ solutions the industry is offering.

It is also interesting that these products use HBM instead of HMC (hybrid memory cube) memory stacks that Intel developed with Micron [link]

For the latest in advanced packaging, stay linked to IFTLE…