Insights From Leading Edge

Monthly Archives: April 2018

IFLE 380 IMAPS Device Packaging Conf Part 3: Yole Updates FO-WLP

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a look at the latest Yole update on Fan out Packaging by Jerome Azemar that was presented at the IMAPS 2018 Device Packaging Conference.

As we have discussed before, fan out packaging can be embedded in laminate or embedded in mold cmpd (EMC) . Chips can be placed face up or down with various options for interconnections.

yole 1-2

Their look inside a smartphone gives an interesting perspective on where fan out packages are being used and where they can be used.

yole 2-2

Yole sees automotive radars as an interesting market for fan out solutions

– fan out used in Rf and radar applications

– since 2015 Infineon has shipped > 10MM Radar IC in eWLB packages

Yole reports that technical challenges still exist for fan out as shown below:

yole 3-2


They see high density fan out (like TSMCs InFO) fan out being in competition in the future for HPC (high performance computing) and AI (artificial intelligence) applications with silicon 2.5D solutions.

While panel production would certainly reduce costs (more units per operation) such technology is not ready and will have large capital equipment costs. They see production being mainly on wafer through 2022.

fowlp iftle 380


CMOS Image Sensor Market

IC Insights Optoelectronic, Sensor, and Discrete report concludes that the CMOS Image sensor market is not approx. the same size and growth rate as the LED business [link]. An interesting comparison…

CIS market

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IFTLE 379 IMAPS DPC 2018: Chip to Wafer Hybrid Bonding

By Dr. Phil Garrou, Contributing Editor

IFTLE has extensively discussed the applicability of the Ziptonix technologies (acquired and now owned by Xperi): ZiBond (oxide-oxide bonding) and DBI (copper-oxide to copper-oxide “hybrid bonding”) [for example see IFTLE 303, “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7” and refs therein]

These technologies have now been commercialized in areas such as COS image sensors, Rf and MEMS. These are all wafer to wafer bonding applications. As of yet, a die-to-wafer process has not been developed for manufacturing, imposing W2W limitations such as the requirement that die sizes match and yields are high.

experi 2-2

At the recent IMAPS Device Pkging Conf in March, Wang of Xperi discussed the “Design, characterization and testing of large area and high density 3D direct bond interconnect which discussed development of such a die to wafer technology.

DBI’s key attribute is the formation of electrical interconnects at low temperatures and pressures as shown below:

experi 3-2

The technology requires highly polished (CMP’ed) surfaces (less than 1nm deviation across wafer surface topology is typical) .

The Xperi goal was expressed as developing a process for HBM memory stacks by stacking 4 double sided DBI memory die with the following attributes:

– throughput – 3000uph                       – no underfill

– no solder                                             – stack consecutively then batch anneal

For die to wafer bonding they followed he following process sequence:

experi 4

The design that was evaluated for a HBM stack contained 10um pads on 40um pitch.

D2W vs W2W electrical test for their test vehicle is shown below:

experi 5

Die to wafer reliability for a 31K daisy chain are shown below:

experi 6

It will be interesting to see whether this data will extrapolate to the fabrication of real HBM die stack in the future.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 378 IBM/DARPA ICECool Program Summary; Apple to Inc use of Apple Chips

By Dr. Phil Garrou, Contributing Editor

The March Issue of Electronic Cooling magazine contains a great summary article on the IBM effort in the DARPA ICECool Program [link]. I recommend reading the full article which I will summarize here.

When today’s standard cooling technology, air cooling with fans, does not meet the required needs, advanced water cooling approaches are examined. Traditional water cooling approaches replace the heat sink with a cold plate that provides more efficient heat transfer. But, because of its electrical conductivity, water cooling requires isolation measures to protect the chip, and requires large channels to cool large high-power die at reasonable pressure drops.

As part of the DARPA ICECool program, seeking to develop appropriate cooling technologies for 3D chip stacks, IBM developed a new chip-embedded cooling approach, utilizing a nonconductive fluid, doing away with the need for a barrier between the chip electrical signals and the fluid. This chip-embedded cooling technology pumps a heat-extracting dielectric fluid into ~100μm cooling channels, between the chips at any level of the stack. The coolant removes the heat from the chip by boiling from liquid-phase to vapor-phase. It then re-condenses, dumping the heat to the ambient environment. Since this system doesn’t need a compressor, it can operate at much lower power compared to typical refrigeration systems.

The dielectric coolant is fed in at the center of the die, moves through radially expanding channels, and exits at the edges of the die. This approach (shown below) provides better energy efficiency and maximum critical heat flux with the resulting reduced flow path.

To modify an IBM microprocessor module for embedded cooling the package lid was removed to expose the processor die, a deep reactive ion etch (DRIE) of the processor die was performed to generate the 120 µm deep cooling channels structures in the backside the processor and a glass die was bonded to the etched processor die to create the top wall of the micro-channels and a brass manifold lid, which provides for coolant supply and return, was bonded to the glass manifold die and the organic substrate using an adhesive. The coolant enters the module and passes through 24 inlet orifices to distribute the flow among the corresponding 24 radial expanding channels as shown below.


The figure below compares the performance of the standard air cooled module with the new embedded liquid cooled module. The cores temperature were measured with coolant inlet temperature in both cases at 25 ºC; a dielectric coolant mass flow rate of 9 kg/hr at a pressure drop of ~11 psi. The temp of the air-cooled processor levels off at around 70 ºC as the system fans speed up (~65%) to prevent overheating whereas the liquid cooled system is running at 40 – 45 ºC. At the highest power operation (4.3 GHz) the reduced operating temperature results in over a 10 watt decrease in the power consumed by the microprocessor along with a significant reduction in fan power (15+W) .


Apple to Replace Intel chips in Macintosh Computers

Bloomberg is reporting that Apple, which has used Intel processor chips in its computers since 1995, is planning to use its own chips in Mac computers beginning as early as 2020 (code-named Kalamata), replacing processors from Intel (link).

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IFTLE 377 μ-Transfer Printing going mainstream?; Heterogeneous Int at IMAPS DPC

By Dr. Phil Garrou, Contributing Editor

OSRAM licenses m-transfer printing from X-Celeprint

IFTLE has discussed m-transfer printing for several years, first with Semprius [ see IFTLE 203 “Apple Acquires LuxVue µ-assembly Technology” ] and then at licensee X-Celeprint [see IFTLE 354 “The Case for µLED Displays”]

We have seen Teledyne using the technology in several DARPA programs and have heard rumors of the technology being used to develop mLED displays.

It now appears that a major player in word wide LED component marketplace has significant interest in the technology because OSRAM now reports that they have entered into a technology and patent licensing agreement with X-Celeprint for their m-transfer printing technology (link)

Exactly how will OSRAM use this technology in their LED products?? We’ll be keeping an eye out and report back to our readers…

Xceleprint 1

μ-transfer printing basics [link]

Heterogeneous Integration Roadmap Update at IMAPS DPC

Starting this week we will begin going over some of the presentations at the IMAPS Device Packaging Conf held every year outside Phoenix, AZ. At one of the keynote presentations Raja Swaminathan of Intel discussed his work on the Bill Chen Heterogeneous Integration Roadmap.

If you read this blog regularly you have probably picked up on the fact that IFTLE has little tolerance for bad nomenclature and/or redundant nomenclature. So, let’s consider the term “heterogeneous Integration” what this means is basically combining (i.e integrating) things that are not the same (i.e. heterogeneous)…i.e. a DRAM memory module is not heterogeneous integration (but would be homogeneous integration) . So is this something new ?? In the 1990s we called them multichip modules. Today that is also called a SiP. Too many terms meaning nearly the same thing for my liking.

But…given that the community has appeared to latch onto this catch phrase lets look at what the roadmap committee is doing about the naming.

Swaminathan makes the point that on package integration is more compact, low power and higher band width than off package connections (see below).

Intel 1-2

In order to improve on the meaningless terms 2.5D, 2.1D etc they are proposing that we consider these as 2D enhanced architectures as side by side active silicon interconnected at high densities using either organic or silicon based interposers.

intel 2-2

So, TSMC’s CoWoS would be 2DS with TSV, ASEs FoCoS would be 2DO chips last and Intel’s EMIB would be 2DS without TSV.

Intel 3

Technologies are compared I terms of density below:

Intel 4

Swaminathan concludes with a slide showing on of the main themes of IFTLE for the past decade “Packaging technologies will become more wafer-fab like.”

Intel 5


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