IBM water cooled 3D IC At the recent CeBIT Fair in Hanover Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM 3D Chip Stacking Project developed at IBM Research – Zurich. Merkel asked him, "Did you take that from Intel?" Palmisano reportedly reply, "No, ours are better”.
[Merkel gets points for pushing IBMs hot button (probably unknowingly) and Palmisano gets points for a sharp response under pressure !]
German chancellor Merkel and IBM’s CEO Palmisano
Their 3D chip stacks are cooled by 50 um micro channel cooling technology . Such liquid cooling reportedly reduces power consumption or the normal cooling fans. The cooling technology was developed by IBM together with the École Polytechnique Federale de Lausanne and the ETH Zurich within the scope of the European CMOS AIC project. Dr. Bruno Michel manages the Advanced Thermal Packaging group at IBM Research – Zurich. The group has pioneered energy-efficient hot-water-cooling and the concept of a zero-emission data center.
The first goal is reportedly to directly stack memory onto the processor. IBMâ€™s 3D technology is reportedly scheduled to appear in its upcoming Power8 processor, planned for 2013, using 28 or 22nm process technology. While the technology is reportedly being transferred to iDataPlex servers, it is expected that it will be a few more years before it is fully ready for production.
ï»¿TSMC Interposer Production in 2012, Making Move into Advanced Packaging
We first started tracking TSMC’s San Jose spring technical symposium in 2008 when TSVs first appeared on their roadmap [ see PFTLE 30, “Foundry TSVs Are a Comin’ – TSMC Makes Their Play for a Bigger Portion of the Pie” In 2009 they reconfirmed their plans for fab based TSV . [ see PFTLE 73, “ TSMC Reconfirms Plans for Fab-Based TSV “]. At this years meeting, last week, Sr VP of R and D Shang-Yi Chiang indicated that they would initially offer silicon interposer technology, which they are currently sampling and plan to have in full production by late 2012.
Perhaps more interestingly, TSMC updated the audience on a theme they first brought up in 2008 when they suggested that they might “in the future” be after a bigger portion of the packaging pie. We recently reported that TSMC would enter the interposer technology and that in fact they were delivering the interposers to Amkor for assembly already bumped, rather than have Amkor do the bumping [ see IFTLE 43, “IMAPS Device Packaging Hilights – 3DIC”] TSMC first put in bumping capacity for 200 mm wafers in 2001 when they installed 15K wafers/mo capacity for business with Altera. They have had limited bumping and WLP capacity since then although they have mainly used their OSAT partners for such operations.
Now TSMC is expanding its bumping efforts. They will ramp up a new 200,000 to 250,000 wafers per month bumping facility in Tainan, are qualifying 100-micron bump pitch lead-free and new copper pillar bump technology at the 28-nm node and are ramping up 28 nm WLP qualification by December targeting the mobile market. Although claiming to still be a “front end company” it is clear to IFTLE that TSMC is making inroads into the packaging business.
UMC Announces 3D Equipment Aquisition
In mid 2010 UMC announced their 3DIC alliance program with Elpida and Powertech Technology (PTI). [see IFTLE 8, “3D Infrastructure Announcements and Rumors” ]At that time, UMCs CTO reported that they expected to be sampling 3D IC solutrions using their 28 nm technology “..in mid 2011) with production slated for 2012. In keeping with these previous announcements, UMC has just announced that they have acquired $19 MM worth of 3D TSV production equipment from Hong Bao Technology (a 73% owned subsidiary)
ï»¿CMOS image sensors continue to overtake CCD
i-Supply reports that in 2011 CIS ( a key applications area for TSV and in the future 3D IC stacking) will surpasses CCD by > 10:1 in both units and revenue.
Image sensor Shimpents and Revenue (i-Supply)
CMOS image sensors for digital cameras, the last bastion of CCD technology, are expected to exceed those of CCD devices in 2013. CMOS sensor advantages include lower power consumption, reduced cost and circuit integration. The lower power consumption of CMOS sensors yields longer battery life. CMOS sensors also allow for the possible inclusion of on-chip peripheral circuits, increasing the integration of electronics and reducing the size of DSCs. CMOS sensors also support backside illumination technology (BSI), enabling better quality imaging in low lighting conditions.
CMOS image sensors shipments for DCS are projected reach ~ 71 MM units, up from ~ 30MM in 2010. CCD shipments are expected to decline to ~ 67 million units in 2013, down from ~ 94MM in 2010. By 2014, more than 85MM CMOS are expected compared to 51MM for CCD.
Digital still camera image sensor unit shipments by technology (MM of units).
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