Insights From Leading Edge

Monthly Archives: June 2012

IFTLE 107 2012 ECTC Part 1 Committees and Awards

The 2012 IEEE ECTC conference was held, as it always is, over Memorial Day weekend this year in San Diego. Attendance was an outstanding 1200+.

The executive committee, which is responsible for all content,  is shown below. (Click on any images to enlarge them.)

[Back row: Steve Bezuk, Pat Thompson, Wolfgang Sauter, Beth Kesser (winner of the IFTLE  name the packaging experts contest !), Bill Moody, Sunil Peking, Alan Huffman, Tom Reynolds                          Front row: Eric Perfecto, Jean Trewhella, Kitty Pearsall, Dave McCann, Rajen Dias, Lisa Renzi]
The committee gave special thanks to two wives who have been helping with registration and anything else the conference needed for over a decade — Lynn Reynolds and Nadine Bezuk:
An important part of every ECTC is the IEEE CPMT awards ceremony. This year’s CPMT officers include : Ricky Lee (President); Jie Xue (Technical VP); Jean Trewhella (VP Conferences); Kitty Pearsall (VP Education); Wayne Johnson (VP Publications) .
The theme of this year’s meeting was "going on safari" (I assume tied to the San Diego Zoo) so that’s a safari hat on Ricky’s head in case you’re wondering.
This year’s award winners included:
 IEEE CPMT Field Award to Dr. Mauro Walker (Motorola – Retired)

As IFTLE has described previously, the Field award is the highest level award in IEEE for any given division, so this is the highest award available in the world for IC packaging. This year’s recipient Mauro Walker has had a long career of accomplishment in the advancement of electronic manufacturing and manufacturing technology in industry, academia and professional societies. His leadership in Motorola in the 1970s and 1980s drove the component packaging miniaturization that was necessary for portable communications such as cell phones pagers and two way radios. He established advanced manufacturing technology centers within Motorola which developed many innovations for high speed surface mount assembly.

He is the previous recipient of the IEEE’s Special Manufacturing Technology Award and the Society for Manufacturing Engineers’ "Total Excellence in Electronic Manufacturing Award." Walker is an IEEE fellow and founder of the IEEE International Electronic Manufacturing Technology Symposium (IEMT).
Having worked on technology introduction programs with Motorola during this time, I can tell you that this is a well deserved award. There was no one introducing technology like bumping and chip scale packaging into consumer products better or earlier than Motorola in those days.  Congrats Mauro!
IEEE CPMT Dave Feldman Award to Dr. Phil Garrou (Microelectronic Consultants of NC)

  The Dave Feldman award is for extended and extraordinary leadership in the IEEE CPMT society. It is named after Dave Feldman who was a key player in Bell labs in the 1950 and 60s and started the ECC (the predecessor  to ECTC) in 1950. I am humbled to say that this year’s winner was yours truly. After the luncheon, a bright eyed 20 something engineer came up to me and asked exactly what you had to do to win an award like this, i.e what made me stand out from the other folks in a position of leadership in this large organization. He probably expected some quick cliche  answer, but instead I bent his ear with some philosophy. But seriously, the two actions that I am most proud of during my Presidency have to be (1) installing 1 man one vote on a global basis. While Rao Tummala certainly drove the global expansion of the CPMT society during his 4 years, when I took over as President our board of Governors still had a European and an Asian representative which the rest of the US elected body "selected" to represent the non US members. After developing enough internal consensus,  I pushed to have non US members select only their own representatives and to have each region represented based on the number of members in those regions. Seems logical enough, but somebody had to actually push to get it done and that was me. FYI – it is no coincidence that our last president was from Germany and our current president is from Hong Kong – we are now truly a global society which was Rao and my original dream. PS – growth in both these areas continues – this year both Europe and Asia representation went up by one BOG member while the US went down by two. (2) the complete ownership of the ECTC. Since I started going to the ECTC in the mid 1980s, I was always confused by the co-ownership (IEEE CPMT and EIA) that existed. As I took over as President this did not clarify itself, but rather became more and more confounding. ECTC was, and is the flagship conference of the CPMT, but it was only partially controlled by our IEEE organization. So my second "quest" was to buy out the EIA. I was not able to conclude this during my term, but after convincing incoming President Bill Chen of the logic in this, we moved forward during his presidency to amicably conclude this transaction. That’s it, although it may seem trivial to you the reader, that’s what I think my lasting stamp on the organization will forever be. 

Sustained Technical Contribution Award – Tseung-Yuen Tseng (Chiao-Tung Univ Taiwan)

  The sustained technical contribution award went to Tseung-Yuen Tseng of National Chiao-Tung Univ in Taiwan where he is University Chair Professor in the Department of Electronics Engineering and the Institute of Electronics. Dr. Tseng’s professional interests are electronic ceramics, nanoceramics, ceramic sensors, high-k dielectric films, ferroelectric thin films and their based devices, and resistive switching memory devices. He has published over 300 research papers in refereed international journals. He invented the base metal multilayer ceramic capacitors, which have become large scale commercial product. Dr. Tseng was elected a Fellow of the American Ceramic Society in 1998, IEEE Fellow in 2002 and MRS-T Fellow in 2009.

Exceptional Technical Achievement Award – Andrew Tay – National Univ of Singapore
Electronics Manufacturing Technology Award – Chin Lee – Univ of California
Outstanding Young Engineer Award – Mudasir Ahmad – Cisco
IEEE Fellows – Mao Jun Fa (china), Yogendra Joshi (USA), Pradeep Lall (USA), Mike Li (USA), Anthony Oates (Taiwan), William Palmer (USA), Enboa Wu (China)
For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………..

IFTLE 106 2012 Symp on Polymers for Microelectronics

This was the 15th year that polymer suppliers and users have met in Wilmington DE to discuss the latest advances in polymeric materials. All of the big boys were there including : HD MicroSystems , Dow, JSR, Asahi Kasei, Toray, Nippon Kayaku (MicroChem), AZ and Hitachi Chemical.

Certainly the most interesting bit of information that I learned about a materials supplier was that Alpha started its business in 1704 making cannon balls… cannon balls to solder balls — now that’s a roadmap for miniaturization!

Certainly the main theme, as you shall see below, was the development of low curing temperature polymers that could come close to matching epoxies curing temp (i.e ~175C) while maintaining improved thermal and mechanical properties.   

My plenary presentation was based on the new Yole report "PolymericMaterials for 3DIC & WLP Applications"

Basically over the last 50 years the industry has developed five  basic chemistries for the microelectronics industry. In chronological order they would be epoxies, siloxanes, polyimides, BCBs and PBOs.

(Click on any of the images below to enlarge them.)

If we look at the properties that are important to all or most functions / applications we find 4 broad categories including electrical, mechanical, thermal and misc. (other).

The half dozen key functions that we want these polymers to fill and the seven wafer level applications that we are looking to use them in are depicted below.

Yole projects a 26% CAGR for WL applications over the next few years which will expand the current market to near $1B with significant expansion of applications other than FC bumping.
Since new materials take decades and 10s of millions of dollars to develop, those in the business of wafer level packaging over the next 5-6 years will basically have products from these 5 chemistries to serve the functions for the listed applications.  

The theme for permanent dielectric suppliers at this meeting seemed to be positive tone aqueous developable dielectrics with sub 200C curing temperatures and resultant low stress. The newer packaging scheme such as eWLB require this evolution in dielectric materials because the wafer substrate is epoxy based and  cannot survive the processing temperatures needed to cure polyimides or most PBO and BCB materials. Also, ICs with embedded memory are very sensitive to process temperatures and survivability drops dramatically with increase in temperatures. Lastly, advanced technology nodes such as 32 and 22 nm use lower-k dielectric materials, which are sensitive to the high stresses generated by higher curing temperatures.
Toray is offering a LT series low-temperature curing,  positive-tone photosensitive PI coating with a 170- 200C curing temp and resultant 13 MPa thermal stress. With a tensile strength = 100 MPA, elongation of 30% and Modulus of 2.5 GPa . While the residual stress is reported as 13 MPa, the CTE is troubling at 70 ppm. Asahi Kasei is offering  BM series PIs which reportedly can cure as low as 200C with a Tg of 220C, a CTE of "50-60" and a stress of 19 MPa . HD Micro reported on a new PBO, 8850, with reported better chemical resistance, which can be cured at 250C. JSR reported on their WPR series dielectrics which for positive tone are cresol based with rubber reinforcement. While they can be cured at 200C and have low residual stress ( 20 MPa), their tensile strength (80 MPa) and elongation (7%) are low for permanent dielectrics.  Dow chemical reported on their aqueous developable P6505 BCB which cures as low as 180C (3 hrs) with a resultant stress of 25 MPa. Most of the properties look like the BCB 4000 series with a notable exception that water absorption has risen from 0.2% to 2% for the new version. 
Toray also introduced a siloxane product to replace acrylics for optical applications such as CMOS image sensors, LCD and OLED displays and solar modules. It is 99% transparent at 400 nm and is much more thermally stable than the typical acrylics.
As a general comment, all of these materials are beginning to look like one another which may or may not be a good thing for the industry. As IFTLE has said many times before, you must determine what properties are most important for your application and choose your dielectric accordingly. 
Next week we begin our coverage of the ECTC conference. For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………….

IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple

TSMC Tech Symp

At the 2012 TSMC Tech Symp in April they revealed Reference Flow 12 which shows 2.5/3D firmly entrenched in the TSMC roadmap.

Recent blogs have discussed TSMCs move into the 3D and advanced packaging area. [see IFTLE 94 “Experts discuss InterposerInfrastructure at IMAPS DPCand IFTLE 102 “3.5D interposer technology could somedayreplace PCBs" — TSMC’s Doug Yu” ]

Indeed TSMC isnow showing slides where only the memory and substrates are coming from external sources, making them a turnkey solution for what they are now calling 3.5D [link].

UMC stays in the game
In IFTLE 88 “Apple 2.5D Rumors; Betting the ranchâ??¦” we drew an analogy of putting new fab production in place to a poker game in the Wild West – or betting the ranch. Well, the recent announcement by UMC certainly had them tossing their chips into the center of the table matching the recent capacity announcements by TSMC and Global Foundries. The UMC 300mm Fab 12A Phase 5 & 6 in Tainan will extend 28nm production. P5 & P6 will provide advanced 28nm, 20nm, and 14nm capacity, and is scheduled for equipment move-in during the second half of 2013. Total cleanroom area is 53,000m2 and will be capable of 50K wafers per month, bringing total monthly design capacity for Fab 12A to 130K wafers. With the planned P7 & P8, the eight phase fab complex will have a total design capacity of 180K wafers per month.
Cumulative capex for UMC’s Fab 12A phases 1-4 is projected at $ 8 billion, with P5 & P6 to add nearly $ 8 billion more. There are further plans for P7 & P8. As we said earlier, only the big time players are sitting at this table. With such investments, UMC is certainly showing that they intend to stay in the game.
 They also announced continued activity in “â??¦ BSI CMOS image sensor, 2.5D interposer, and 3D IC TSV to provide a truly comprehensive, leading foundry technology platform”  
Rumors from the ECTC
The IEEE ECTC meeting was last week and for those of you who are unaware, it is the number one show for advanced packaging in the industry. 2.5/3D has grown steadily at this conference and it now appears to be nearing 50 % of the ECTC content [ 50% of 6 parallel sessions for 2.5 days] . There were no major announcements at the meeting, but there were some interesting rumors. My filtering criteria is that I must hear the rumor at least twice from separate sources before I report it on to you.  None of these could be substantiated by the parties involved, but that is not surprising.
 IBM Power8 processor
IFTLE has reported before that rumors were swirling that a future generation of the IBM power chip processor would be using a 2.5D interposer configuration. Very strong, multisourced rumors at ECTC persist that the Power8 is currently undergoing testing in IBM servers and we could be hearing about this major interposer announcement “soon” .
If your like me, you have been waiting for 5+ years for the imminent 3D announcement from Intel. Recall that we have been told that the technology is ready but it would be up to the product departments as to when to introduce it. Well, not so good news here. The rumor going around is that we are probably looking at 2017 when 450 is introduced. (Don’t shoot me I’m just reporting the rumor. ) If anyone from Intel would like to deny this and give IFTLE better information please send me an email.
Apple / TSMC / Samsung
Back in IFTLE 88, “Apple 2.5D rumorsâ??¦â??¦” (which I’m told was the most read IFTLE blog of all time) we discussed the fact that TSMC and Samsung are in competition for the next generation , the A6, processor for the Apple iPod, iPad etc.. Although everything is hush, hush, it is clear that TSMC is at least developing prototypes based on their interposer technology. It is unknown whether Samsung is doing the same (but we can hope so).  Two opposing  rumors were making the rounds at ECTC. Rumor 1 had Samsung about to make a 2.5/3D announcement, but rumor 2 had Samsung developing an “unknown technology” that negated the need for TSV and leading them to the conclusion that 2.5/3D would not be needed in the future. The Samsung clamp down on the release on any information on 2.5/3D remains â??¦hermetic . Yes these could in fact be the same rumor, but I, for one, hope not.
Lots more from the ECTC over the next few weeksâ??¦â??¦â??¦â??¦â??¦..
For all the latest on 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦.

IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper

Continuing with key presentations from the 2012 IMAPS Device Packaging Conference in Ft McDowell AZ.

Tezzaron Process Technology
Bob Patti showed off two Centip3De, a 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM from the Univ of Michigan and the 3-D MAPS, a massively parallel processor using 64 custom cores stacked with a block 256 kilobytes of scratch pad memory from Ga Tech. For more details on these see IFTLE 93, "2.5/3D at the 2012 ISSCC".

(Click on any of the images below to enlarge them.)

Amkor Discusses 2.5/3DIC

Amkor’s Ron Huemoeller reported that 3D vertical stacking is:

memory and application processor driven
– today focused on 28 nm CMOS and moving to 22 nm
– application processors are near exclusively moving to OSAT finished wafer process flows
Whereas 2.5D Interposers are:

–  network, CPU and GPU driven
…….. mother boards reduced from 10 to 6 layers
…….. reduce chip mask layers
…….. smaller x, y dimensions
– focused on large package bodies (40 -90 mm , near retical sized Si)
  both foundry and OSAT wafer flow processes being used

He sees both dis-integration of large logic blocks and separation of functions

– allows focus of specific functions which require  leading process nodes
– improves wafer yield
– reduces time to market
– reduces mask layer count at advanced process nodes

Concerning the interposer supply chain:

– laminate (which can theoretically be delivered in large panel format (i.e. 500 x 500 mm ) are being investigated by several "elite substrate manufacturers" [ Unimicron, DNP, Shinko, Kyocera]. Limited to 8 um L/s and 40 um vias on 85 um pads today. 5 um l/s will require stepper and better resists which change the economics. 5 um L/S thought to be many years away. Latency issues will limit adoption as will limitations in va/pad design rules.

– glass can be delivered in large panel or wafer format. Several glass companies [Hoya, Corning, AGC] are investing in capability to support glass interposer technology. Glass faces challenges for CMP / damascene processing.

– silicon in 200 or 300 mm several companies supporting silicon interposers in idle foundry space on legacy node technologies. Amkor finds only 3 foundry players committed to delivering "fine featured" interposers [ TSMC, GF, UMC] with TSMC the only one currently delivering in any quantity.

According to Amkor several foundry sources are interested in manufacturing Si interposers and a couple are already delivering fully functional wafers. Currently design rules  "are aggressive" i.e. less than 2 um L/S and 5 um vias.

Amkor indicated that the predominant interposer designs are what IFTLE has been calling "fine featured" as follows:

When looking at TSV products expected to enter the market in the next few years, Huemoeller offered the following roadmap.

TI Promotes Cu WB

TI has recently announced that all 7 TI internal assembly and test sites are now converted to Cu WB. 6.5B devices have been shipped in Cu WB with conversions continuing. TI which started their Cu WB studies in 2003 are in HVM at the 65 node and have qualified down to the 45 node. 50% of all their interconnect wire is now Cu.
Analog, wireless and embedded products in BGA and leadframe packages are all qualified. Cu shows less wire sweep during package molding and since it has better inherent thermal conductivity it shows better battery life. Next TI will be looking at "high rel" applications such as automotive, military and down hole drilling with Cu wirebonding.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………….