Those of you that are readers of SST know from the editorials and blogs of Editor Pete Singer that the ConFab is Solid State Technologyâ€™s annual conference and networking event. This year, it was held in June 23-26 in Las Vegas.Â The overall theme of this yearâ€™s conference is â€śFilling the fabs of the future.â€ť IFTLE put together two sessions on packagingÂ which were jointly sponsored by IEEE CPMT and ConFab.
The most significant packaging announcement from the ConFab was SPIL announcing that they have put dual damascene in place and are ready to start supplying high-density interposers to the industry.
Sony CMOS Image Sensor 3D Stacking
Fellow bearded blogger Dick James of Chipworks, in his presentation â€śInside Todayâ€™s Hot Productsâ€ť showed some great X sections of the Sony IMX135 13 Mpixel CMOS Image sensor. One of the first stacked image sensors it consists of a 90nm back illuminated sensor bonded F2F with a 65nm image processor.
IBM Orthogonal Scaling
Subu Iyer, IBM Fellow, lectured on his theme of â€śorthogonal scaling.â€ť His premise is that classical silicon scaling is saturating and we need orthogonal approaches to â€śscale all aspects of the system including footprint and power.â€ť Subu sees scaling continuing down to the 7nm node, butÂ â€śthe cost per transistor has begun to saturate.â€ť
He predicts that the next component of Advanced System Integration will be 3D Integration:
– large interposer platform for heterogeneous integration
– Die Stacking
– stacking of logic die (high and moderate power)
– stacking of memory die (low power)
– Wafer level stacking
His example of stacked memory is the Micron IBM program on stacked memory:
TI Thins Down Packaging
Devan Iyer, worldwide Dir. of Packaging for TI showed the thickness progression from the 1.75mm SOIC to the 0.075mm PicoStar-2G
Iyer points out that while Package families areÂ proliferating, each package type has a â€śsweet spotâ€ť combination of cost, performance, form factor and reliability, driven by:
â€˘Electrical speed, power distribution and noise immunity
â€˘Thickness, weight, PCB area consumption
â€˘Board level reliability (BLR, drop)
â€˘Technical maturity vs. risk in high-volume manufacturing
â€˘Compatibility with Si process
Anderson of STATSChipPACÂ points to smartphones and tablets driving our industry right now.
For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.