Insights From Leading Edge

Monthly Archives: July 2014

IFTLE 202 ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel

By Dr. Phil Garrou, Contributing Editor

Dave Anderson, CEO of Novati talked about “More-than-Moore, Advanced Packaging and Creating Game-Changing Innovation.” In keeping with the main theme expressed by IFTLE for several years, Anderson echoed, “Most companies can’t afford to continue to pursue Moore’s Law scaling” and offered “More-than-Moore” as a product customization route for the future.

Andrew Kim of Philips Lumileds updated attendees in “Trends in LED Manufacturing.” (As you may recall IFTLE and its incarcerated spokesman Lester Lightbulb are not strong supporter of LED replacement  of the incandescent bulb, i.e. see IFTLE Lester Lightbulb.)

Kim presented a “very simplified” process sequence for LEDs manufacturing. (“Wow that sure should be cheaper and better for the environment than a tungsten filament bulb.” – Lester) In addition, as we have shown before, the new light sources are not only the “electroluminescent emitter,” but a far more complicated circuit of PCB and components [see IFTLE 63 “Bidding Adieu to Lester the light bulb”]

Limileds 1


Kim sees the following options developing for substrate alternatives.

– Sapphire: currently dominant, current substrate cost for larger sizes

– Silicon: Manufacturing and performance

– GaN on GaN: Cost and value proposition

– SiC: Single LED user with captive source

Evidently the DOE game plan is still to reach $8 / bulb by the early 2020’s. (“Wow that will make it only 16X the cost of an incandescent bulb” – Lester)

lumileds 2


LEDs certainly offer new form factors for light and in the future will allow creation of devices that we are not today thinking about.  IFTLEs issue with LED lighting is with how it was sold to the consumer as a saver of power and a saver of cost. IFTLE arguments have been presented previously and can be found here [link].

By the way, we are now more than three years into our single bulb testing which was started in Aug 2011. The CFL was dead in < 10 months but the LED and the incandescent are still burning bright 3 years into the testing. Remember the incandescent cost me only 50 cents.

Fellow SST Blogger Dick James from Chipworks shared “Inside Today’s Systems & Chips: A Survey of the Past Year”. During their reverse engineering of the Apple iPhone 5s, Chipworks identified the CMOS image sensor as Sony’s  AW34 5399.

chipworks 1


IEEE CPMT Packaging Session


Bill Chen of ASE put together an Advanced Packaging panel to update ConFab attendees on the latest packaging advances.

packaging group


Garrou (IFTLE), Chen (ASE), Huemoeller (Amkor), Bezuk (Qualcomm) and Black (AMD)

The presentations of Amkor, Qualcomm and AMD have been reviewed recently by IFTLE [ see: “IFTLE 179 GaTech Interposer Conf: Amkor, GlobalFoundries”; “IFTLE 186 IMAPS Device Pkging Conf: Qualcomm, Prismark”; “IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP”.

As part of my presentation, I looked at the status of a few of the 3DIC rumors that we have discussed on IFTLE, which didn’t come true and the current status of announced products including Hynix stacked memory, Microns HMC stacked memory and graphics modules from Nvidia. Memory is now happening, so hopefully the rest of the products will be coming soon.

Garrou 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 201 2014 ConFab: Global Foundries; IBM, G450C

By Dr. Phil Garrou, Contributing Editor

Yes, we have now passed numero 200 on what I shall self proclaim the #1 informational blog for 3DIC and advanced packaging on the internet! Again, my thanks to Pete Singer for continued support.


Now that you have taken a look at us, let’s take a look at some of the presentations at this year’s ConFab.  Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry.

Emerging applications will include:


1. Computer vision

2. Augmented reality

3. Concurrent application and modem operation

4. Gesture recognition

5. Medical applications

6. Contextual awareness

7. HD video and games

8. 3D camera and 3D display

9. Multiple concurrent displays

10. Multiple concurrent audio and video CODECS

Kengeri concludes that “the semiconductor industry is challenged on the Economics of technology scaling.” Cost of building a new leading edge fab continues to escalate while capex / wafer is increasing at a rate of 38%.

Click to enlarge.

Click to enlarge.

In addition, ROI is delayed due to increased investment requirements and longer time to volume.

Click to enlarge.

Click to enlarge.


GF also offered some interesting insights into the industry landscape.

Click to enlarge.

Click to enlarge.

Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Patton confirmed that scaling beyond 22nm will require alternative device structures and new material innovations.


Click to enlarge.

Click to enlarge.

Beyond silicon, packaging and board innovations are required to continue to miniaturize. IBM points to interposers and die stacking to do this.


Click to enlarge.

Click to enlarge.

Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

G450C is a public/private program based at the College of Nanoscale Science & Engineering in Albany with goals of :

–  Driving effective industry 450mm development

–  Focus on process & equipment development

Members include Intel and the major foundry players and for now IBM (rumors of their acquisition by GF remain rampant).

G450 1

The consortium sees the following changes coming between 300mm and 450mm.

G450 2

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 200 Semicon West Suss Workshop: Laser Debonding and KLA Tencor platform for WLP inspection

By Dr. Phil Garrou, Contributing Editor

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP.

Stephan Luetter compared the various temp bonding technologies and their current focus on excimer laser assisted release.   The EDL-300 is their eximer laser debond module which rasters the wafer with a 12x 4mm laser beam. Carrier is lifted of with a vacuum gripper with close to zero mechanical lift-off force. A requirement for laser assisted debonding, is that it uses a glass carrier wafer to allow transmission of the laser light. Suss has concluded that the new materials and simpler process flows allow cost of equipment reduction in the range of 1.5-3X.

Suss temp 1


The Suss open platform program supports 10 materials suppliers and 4 laser assisted RT debonding processes (including 3M, Brewer, Dow and HD Micro).

suss temp 2


Kim Arnold of Brewer introduced their 3rd generation temporary bonding solution BrewerBond which makes use of a laser assisted room temperature debond process.  Brewer who has been supporting the 3DIC infrastructure for a decade has introduced several product families to meet their customer needs. Each generation has increased throughput and thermal stability better allowing backside processing at higher temperatures.

brewer 1


The BrewerBond process makes use of a light sensitive layer which is decomposed during debonding with a 308nm excimer laser. Arnold indicated that development of a gen 4 product with higher throughput and higher thermal stability is underway.

Mark Oliver of Dow Chemical discussed their laser bond release process. Laser debonding at 308nm is shown below. The adhesive ends up on the device wafer side and is removed with a simple tape peel.

dow 1


Dow also proposed the use of temp bonding to deal with warping in technologies such as fan out WLP.

dow 2


Sood of KLA Tencor announced their CIRCL (Concurrent Inspection and Review Cluster)  platform to address inspection requirements for advanced WLP.

KLA Tencor 1


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 199 Omnivision Roadmaps 3D stacking for CMOS Image Sensors; IC Insights Details Trends Shaping the IC Industry

By Dr. Phil Garrou, Contributing Editor


Since Toshiba started using backside TSV in 2008 we have been anticipating  stacking of separate functions in true 3DIC fashion. Last summer, Sony announced such a structure.  [link 1]

Recently, at the  image sensors conference in London, Dr. Howard Rhodes, CTO of Omnivision, gave an keynote entitled “The Future of CMOS Imaging” where he expounded on the advantages of stacking and the separation of the imaging function from the logic function.

fig 1



Of special interest are Rhodes comments on “stacked CIS” which he calls “replacing the BSI Si substrate with logic.” Their roadmap shows Omnivision moving from wafer bonding with simple oxide bonding to “hybrid bond stacking with simultaneous bonding of oxide and Cu contacts to 3 wafer stacking where sensors, ISP and memory are fabricated separately and stacked.

fig 2


Longtime readers of IFTLE will recognize that Gen 1 “Oxide-oxide” bonding is the technology Sony licensed from Ziptronix in 2011 [link].

“Hybrid bonding” is the term commonly used to describe the patented Ziptronix DBI process where oxide and copper (or other metal) bonding occurs simultaneously [link], so one should expect to see more Ziptronix licensing in the future.

IFTLE would guess that there will be further licensing in Ziptronix future.

IC Insights

At the recent SST ConFab in Las Vegas Bill McClean shared his annual report on  “Major trends shaping the future IC Industry.” IC insights reports that recent growth in the IC industry has been mainly in memory.

fig 3


For the first time in 2013, communication surpassed computers in terms of market share.

Fabless sales are now 29% of total IC sales with the US is holding its ~70% market share of fabless market sales which it has had since 2010.

fig 4


The bulk of capex spending is being done by the major players, i.e. the ones who appear set to move forward to lower nodes (1-7 in the chart below).

fig 5


Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.

fig 6


A look at capital spending by region shows Japan and Europe falling for behind with a combined sub 10%.

fig 7


r all the latest on 3DIC and other advanced packaging, stay linked to IFTLE…