Insights From Leading Edge

Monthly Archives: July 2017

IFTLE 345 Toshiba 1Tb Flash with TSV; TSMC CoWoS expansion & 2nd Gen InFO; Samsung Foundry takes aim at TSMC

By Dr. Phil Garrou, Contributing Editor

Time to catch up on some very important industry activities…

Toshiba – 3D flash memory with TSV

Toshiba has announced development of its BiCS flash three-dimensional (3D) flash memory utilizing through-silicon via (TSV) technology [link]. Shipments of prototypes will begin in June 2017, and product samples will be shipped in the second half of 2017. Prototypes were shown at the 2015 Flash Memory Summit.[link 2]

Toshiba reports that by combining a 48-layer 3D flash process and TSV technology has allowed Toshiba to successfully increase product programming bandwidth while achieving low power consumption. The power efficiency of a single package is approximately twice that of the same-generation BiCS flash memory fabricated with wire-bonding technology. TSV BiCS flash also enables a 1-terabyte (TB) device with a 16-die stacked architecture in a single package. The 1 Tb 16 chip stack measures 14 x 18 x 1.85mm.

Toshiba expects to commercialize BiCS flash with TSV technology to provide an ideal solution in respect for storage applications requiring low latency, high bandwidth and high IOPS/Watt, including high-end enterprise SSDs.


TSMC – Expanding CoWoS Capacity?

Digitimes reports rumors in Taiwan that TSMC will expand its CoWoS (Chip on Wafer on Substrate) packaging and testing capacity to fill increasing orders from Nvidia and Google. The capacity expansion will reportedly be at the IC packaging and testing plant in Longtan Science Park (purchased from Qualcomm in 2014) where InFO packaging is currently manufactured. TSMC has not confirmed this expansion.

Reportedly, increasing orders from Nvidia and Google for high-end packaging and testing of their AI Chips has fully occupied TSMC’s existing CoWoS process capacity, driving the company to expand.

Nvidia has moved from 16nm to 12nm for fabricating its Volta-architecture GPU chips. Google has contracted TSMC to carry out wafer foundry services for it’s second-generation Tensor Processing Units (TPU2) using 16nm process technology, as well as backend packaging and testing.

TSMC – 2nd Generation InFO packaging for 7nm node

Digitimes also reports that TSMC’s integrated fan-out (InFO) wafer-level packaging technology will enter its 2nd generation, and be used for their 7nm FinFET process technology. Digitimes notes that this makes it unlikely that Samsung will be able to regain AP orders for Apple’s iPhone, since InFO makes TSMC’s 7nm FinFET technology more competitive than Samsung’s. [link]

Samsung – plans to triple foundry market share

Reuters reports that Samsung plans to triple the market share of its contract chip manufacturing business within the next five years. [link] E.S. Jung, executive VP of the foundry division, told Reuters that they want a 25 percent market share (would be #2 in market share) within five years and will seek to attract smaller customers in addition to big-name clients to fuel the growth.

Samsung first announced that they were considering separating their contract chip manufacturing organization (foundry business) last fall [link]

They finally announced the spin off its foundry operation from the System LSI division to create an independent business unit this past May. This will change Samsung’s current organization consisting of memory and system LSI into three entities including the foundry business.[link] The current foundry business is estimated to be ~ a $4.75B operation.

Research firm HIS reports that in 2016 TSMC held a 50.6% market share, GlobalFoundries 9.6%, UMC 8..1% and Samsung Foundry 7.9%

Samsung says it will start manufacturing 7nm chips using EUV litho tech in the second half of 2018.


IFTLE has discussed for years that Samsung, if they ever chose to, could become the number 2 foundry supplier in the world…well, now they choose to. This is probably bad news for GlobalFoundries and UMC. The question now becomes will Intel do the same. Intel, in the past few years, has put their “toe in the water” but has never really committed to a foundry business. Will this move by Samsung force their hand?

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 344 ECTC 4: Reliability Studies of 2.5/3DIC – Cisco, Infineon, Siliconware

By Dr. Phil Garrou, Contributing Editor

Continuing our look at presentations from ECTC 2017.

Cisco – Challenges of 2.5/3D

Li Li of Cisco gave a nice presentation concerning “Reliability Challenges in 2.5D and 3D Integration”

Compared with traditional 2D IC packaging, the emerging 2.5D and 3D IC integration involves several new elements in design, manufacturing and supply chain processes. These new elements include:

cisco 1


Let’s focus on one area that Li discusses that has for the most part gone under the radar since it is usually not addressed by back end practitioners – gettering. For further info on this topic IFTLE refers you to the work of Koyanagi and c0- workers at Tohoku Univ who have studied the impact of copper contamination on memory retention.

The devices formed from the thinned silicon wafer are more easily affected by metal impurity contamination and crystal defects. Because the Intrinsic Gettering (IG) region and the Extrinsic Gettering (EG) layer in the silicon substrate for gettering metallic contaminants are removed during the wafer-thinning process for the 3D IC fabrication. Potential Cu contamination from Cu TSVs is another concern that can further degrade the device reliability if the barrier for the Cu TSV is not designed and fabricated correctly.

Fig. 2 shows schematically the effect of IG layer and the potential risk of metal (Cu, Au, etc.) contaminants diffusing into the active region and cause device degradation.

cisco 2

Intel has reported Cu contamination from die backside causing high pin leakage after Unbiased Highly Accelerated Stress Testing and High Temperature Storage testing. To prevent Cu contamination from backside, an Ar ion implantation for Cu gettering and a SiN barrier was proposed.

Infineon & Nanyang Univ – Reliability of Copper TSV

Infineon and Nanyang reported on the “Reliability Evaluation of Cu TSV Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis”

The integrity of Ti barrier and SiO2 dielectric liner were evaluated via electrical characterization after being subjected to different stress tests such as high temperature storage, temperature cycling and electrical biasing to detect barrier and dielectric liner degradation in a the structure.

TC -65/150 °C up to 2000 cycles was performed on the structures to study the extent of barrier degradation by thermomechanical stress induced by TC. After electrical biasing, an increase in the inversion capacitance was observed in the C-V curve indicating Cu ions presence in the dielectric liner. It is suggested that the cracks formed after TC stress may have propagated within the Ti barrier. This can eventually lead to the drift of Cu ions into the dielectric liner under a sufficiently high E-field which acts as an external driving force for Cu ions to drift through the degraded barrier and cracks.

Siliconware – Warpage in 2.5D Modules

Siliconware described their “Warpage Study of Large 2.5D IC Chip Module”

SPIL lists four processes for 2.5D IC modules: Chip on Chip, Chip on Substrate, Chip on Wafer first (CoW-first), and Chip on Wafer Last (CoW-last). In this study, CoW-last was studied. CoW_last means the die are stacked on interposer wafer after the interposer is fully processed including frond side u-bump and backside via revealing (BVR), backside re-distribution layer (RDL) and C4 or Cu pillar bumping.

They found that for some specific designs, the area of multiple top dies are smaller than interposer, which produces empty area on interposer. This makes for unbalanced chip module stress and worsens chip module warpage.

Therefore, they propose a dummy die (DAF) structure(s) to fill up empty area on interposer. In this study, two dies are attached on interposer, as shown in the fig below. The thickness is the same as top die thickness.

spil 1

Underfill and molding compound

They found that a method for warpage improvement is to decrease the underfill volume by the design of lower bump/cu pillar height. Generally, high bump height provides the tolerance for warpage compensation because of more solder volume, and also enhance bump stiffness by low modulus underfill.

Assuming there is no reliability effects to low bump height, the underfill during cooling process acts a buffer material for stress releasing, but induces higher chip module warpage. From experimental results, when UF volume reduces 31%, the warpage between chip module and substrate can be reduce 10% at room and high temperature. “To decrease the volume of high CTE underfill really can improve the chip module warpage”. IFTLE reads this as meaning don’t make the bump/copper pillar higher than necessary to achieve the required reliability or it will negatively affect the warpage.

In terms of molding compound, the module with molding compound successfully negates the effects of CTE mismatch and leads to warpage reduction of 87% at high temperature.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 343 ECTC 3: Materials and Processes: Tohoku, Hotachi Chem, Samsung

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 2017 ECTC.

Tohoku Univ – Low CTE Underfill

Kino and coworkers at Tohoku Univ presented their data on the “Remarkable suppression of local stress in 3DIC by MnN based filler with large negative CTE”.

Generally, CTE of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips, as shown in Fig. 2 below. Such local bending stress would affect transistor performance in thinned IC chips. Kino found that they could suppress the local bending stress by decreasing the CTE difference between the underfill material and the microbumps.

tohoku 1

In general, silica, is usually used in underfill material to reduce the CTE of underfill material. A high concentration of filler is required to reduce CTE as low as metal microbumps. However, it is difficult to use the conventional filler for 3D IC with fine pitch microbumps since a high concentration of filler in underfill material increases the viscosity. They propose to use negative-CTE material as the underfill filler to suppress the local bending stress. They used manganese nitride-based material which has large negative-CTE of -45 ppm/K at the temperature from 65 to 100°C. Results indicate that negative-CTE filler can suppress the thinned Si chip bending more than 50% compared with SiO2 filler. 

Hitachi Chemical – Expanding Film for WLP Sidewall Protection

Honda and co-workers from Hitachi Chemical discussed “Expanding film and process for high efficiency 5 sides protection and FO-WLP fabrication.”

WLP is well suited to mobile devices which require small, thin and light bodies. Fan in WLP (FIWLP) is fabricated by building up redistribution dielectric and metal layer on device wafer and attaching ball, and then it is diced to singulated packages. Device semiconductor die sides are exposed in such a FIWLP. The FIWLP fabrication process needs a wide die gap between die for molding compound and to dice, while leaving the molding compound on the die side wall for the protection.

To get the greater productivity and enhance the usage of the device area in the wafer, an expandable film and a novel process have been developedas shown below in fig 2. The film / process can also be applied to a die first type FO-WLP fabrication. Elimination of the die re-placement step can make the FO-WLP fabrication process simpler and less costly.

hitachi 1

The 5 sides protection fabrication process is composed of 7 steps as illustrated in Fig. 2. The

expanding film with diced-wafer was put on the expander and the film expanded. After that the film is fixed to the grip ring , the film is cut out along the outer rim of the ring. After the singulated dice were transferred to the carrier with keeping the expanded die gap, the grip ring was removed. Then the expanding film was removed from the carrier. After over-molding, the molded wafer was singulated by dicing and 5 side protected packages were obtained.

The stress-strain curve of the film was optimized so that the die gap becomes large. Moreover, the die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap after expansion, the standard deviation was about 0.05 mm. Furthermore, the film was applicable to die sizes 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm.

Samsung – Compression Molding Encapsulants for FOWLP

Kwon and co-workers discussed “Compression molding encapsulants for wafer-level embedded active devices”. Challenges that FOWLP packaging technology is confronted with include wafer warpage, die shift/protrusion, and board level reliability. A solution to wafer warpage is considered crucial for successful subsequent wafer processing.

They propose to use a bilayer test structure with silicon wafer and epoxy molding compound as a standardized evaluation vehicle. Each layer is 300 μm thick. To further standardize testing, the molding conditions are fixed at 135 °C x 600 sec with a post mold cure of 150°C x 2 hrs. By standardizing the test vehicle and processing conditions, warpage behavior between mold compounds can be directly compared, and any observed differences are solely caused by the EMC.

Various parameters influencing wafer warpage were screened by the simulated calculation. Among all these parameters, Young’s modulus, CTE, and Tg have a significant effect on the controlling warpage. Generally, wafer warpage is reduced by lowering the Young’s modulus and CTE, and increasing the Tg. Although concurrent optimization of Young’s modulus, CTE, and Tg of a mold compound’s properties is very difficult because of tradeoffs for modifying each component, they developed new compression molding compounds with both low Young’s modulus and CTE, with relatively high Tg.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 342 2017 ECTC part 2: Chip Embedding at Infineon; UCLA SuperCHIPS

By Dr. Phil Garrou, Contributing Editor

So, before we start updating on the latest technologies at 2017 ECTC a quick update on granddaughter Hannah. Long-time readers of IFTLE may recall her early pic from Halloween 2010…


I know this isn’t a sports blog, but be patient with the proud grandpa. This spring, as she approached her 13th birthday and decided to start running track in Jr High. She quickly performed to the point of taking over school records, but really that’s just a little Jr High in Houston the 5th largest city in the USA.

hannah 2

She soon got a call from Track Houston. For those of you who understand USA sports, consider this one of the USAs best AAU track teams. Historically, Houston has won 40 AAU National Junior Olympic championships with Track Houston winning 16 of those. This IS the big time for runners. You can read about them here [link].

Hannah made the 13/14 yr old team and started running against real competition around Easter in the 100m and 400m events. They say a picture is worth a thousand words, so I will leave you with this link to a 24 second YouTube video someone loaded of one of her best races. That’s her in lane 7. If I recall correctly this was run at the Rice Univ track in Houston.

For a guy who grew up playing stickball in the streets of Hell’s Kitchen, all I can say is “You’ve come a long way baby…” 

CHIP Embedding at Infineon

As we said in IFTLE 236 Embedded Packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infrastructure such as FOWLP and (2) those based on a PWB/PCB laminate panel infrastructure.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.

Embedding chips into laminate is a technology that has not quite caught on yet although recent announcements like ASE and TDK’s 2015 agreement for a JV (ASE Embedded Electronics Inc.), based in Kaohsiung, to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded Substrate) technology are making it look much more commercially likely[link]. SESUB is a high-end substrate technology where thinned semiconductor chips are embedded in laminate substrate with copper interconnection down to 20µm minimum L/S.

At the recent ECTC in Orlando Infineon Regensburg reported on “Laminate Chip Embedding Technology – Impact of Materials Choice and Processing for very Thin Die Packaging”. The laminate embedding process consists of elements from conventional packaging technology followed by PCB process steps and dedicated chip embedding process steps. The process flow shown below is a chips first embedding technology.

Infineon 1

The process starts with die attach on a structured or unstructured copper leadframe. After die attach the copper lead frame is roughened to ensure adhesion of the laminate to the leadframe. Any process induced reduction of copper thickness must be compensated for by providing sufficient layer thickness allowance. Die positions are measured before the lamination process ( die shift compensation), leadframe strips are formed into a panel, laminated with pregreg and terminated with roughened copper sheet . Vias are defined by structuring the outer copper foils (drilling or photolith) . The via filling process consists of > 10 wet chemical process steps (desmear, activation, plating etc.).

Both unfilled resin coated copper (RCC) and highly filled prepreg were tested as laminate. Temp cycling (-55 to 150C) and HTT (150 C) show degredation of the RCC built structures, due both to cracking at the RDL corners and high leakage current.


For previous discussions of this technology see IFTLE 301 “Are Silicon Circuit Boards in our Future?”

In their latest presentation at ECTC, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” Subu Iyer and his group at UCLA describe the performance and power benefits of their fine pitch integration scheme on a Silicon Interconnect Fabric (Si IF). They propose a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet (chiplet) to interconnect fabric assembly. They show dramatic improvements in bandwidth, latency, and power are achievable through such a integration scheme where small chiplets (1-25 mm2) are attached to a rigid Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 µm) and short inter-die distance (50-500 µm) using solderless metal-to-metal thermal compression bonding (TCB).

With fine interconnect pitches (<10 µm), their scheme reportedly can achieve > 5-25x improvement in data bandwidth. This can improve system performance (>20x) when compared to PCB-style integration and may even approach single die SoC metrics in some cases. Furthermore they claim the protocol is simple and non-proprietary. They apply the scheme to heterogeneous system integration using a chiplet based assembly method and show significant reduction in design and validation cost.

ucla 1

They see the technology as offering a platform for system scaling. The technology aims at elimination of the use of solder by direct metal-to-metal thermal compression bonding between metal pillars on substrate, to metal pads on the chiplets. This allows them to scale down the interconnect pitch down to 2 -10 μm as the solder extrusion is no longer a limitation. They also remove the packaging of individual chiplets and place the dies directly on the Si IF with inter-dielet spacing of less than 100 μm. Thus, their data links can be much shorter (i.e. 50- 500 μm).

Analysis were done for 2 μm and 10 μm interconnect pitch with pillar diameter being half the pitch and trace width of 1 μm. SuperCHIPS provided a protocol based on fine pitch fine integration of system where the inter-dielet spacing is ~10-20x smaller than the conventional packaged systems on PCB. The fine pitch interconnects provide ~15-80x more number of I/O pins compared to BGA interconnects and ~2- 10x more compared to copper micro-bumps. Table III is presented to show comparison of SuperCHIPS vs conventional packaging:

ucla 2

Their design approach is to partition the system into chiplets that can be heterogeneously integrated on the Si-IF. This chiplet assembly approach allows them to choose heterogeneous chiplets from different technologies, nodes and materials leading to a high probability of chiplet and IP reuse.

For all the latest on Advanced Packaging, stay linked to IFTLE…