Insights From Leading Edge

Monthly Archives: July 2018

IFTLE 392 Chiplet Technology Discussed at DARPA ERI Kickoff

By Dr. Phil Garrou, Contributing Editor

IFTLE readers are well aware of the Electronic Resurgence Initiative (ERI) [ see “IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law”]

With “Moore’s Law,” which has guided the electronics industry for more than 50 years being challenged on both technical and economic grounds, the defense department is putting $1.5 billion into projects that could “radically alter how electronics are made.” [link]

Investments will support R&D in the areas of  Architectures, Design, and Materials and Integration. It is hoped that investments in these 3 thrust areas will lead the next wave of U.S. semiconductor advancement.

DARPA kicked off the initiative and revealed some of the winning proposals July 23-25 in San Francisco.


  • The goal of the Software Defined Hardware (SDH)program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms.

Intel, NVIDIA, Qualcomm, Systems & Technology Research, Georgia Tech, Stanford Univ, U Michigan, U of Washington and Princeton Univ were selected for the SDH program

  • The goal of the Domain-specific System on Chip (DSSoC)program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O).

IBM, Oak Ridge National Labs, Arizona St Univ and Stanford Univ were chosen for the DSSoC program


  • The goal of the Posh Open Source Hardware (POSH)program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs.

Univ of California,San Diego, Northrop Grumman, Cadence, Xilinx, Synopsys, Univ of Southern California, Princeton Univ and Sandia National Labs were selected for the POSH program.

Materials & Integration:

  • The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC)program is to develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures utilizing U.S. fabrication capabilities.

Georgia Tech, Stanford Univ, MIT and Skywater Technology Foundry were chosen for the 3DSoC program.

  • The goal of the Foundations Required for Novel Compute (FRANC)program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures.

HRL, Applied Materials, Ferric, UCLA, Univ of Minnesota and Univ of Illinois at Urbana-Champaign have been chosen for the FRANC program.

….and……….. CHIPS has now been included under the ERI umbrella

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

The CHIPS program envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. The program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.

Instead of building complex SoC on silicon the CHIPS concept sees future systems where each function is made separately (chiplets) and are then connected together on a larger slice of silicon by high-bandwidth interconnects. One of the challenges will be getting these chiplets to communicate properly and do so at a speed and energy cost that’s close to what they’d be if the system were all one piece of silicon. Interconnects using the standard will have to be capable of handling a lot of data without using much energy. It is estimated that it will have to cost less than 1 pico-joule to move a bit and be capable of moving 1 terabit per millimeter.

At the ERI kick-off, Intel CTO Mike Mayberry ,who is  VP and managing director of Intel Labs and holds responsibility for Intel’s global research efforts in computing and communications, revealed that Intel will provide their Advanced Interface Bus (AIB) technology, to program participants, royalty-free to help link chiplets together. AIB is a standard communications interface made for connecting different dies (chiplets) in the same package. Intel already uses AIB in 2.5-D packages such as the company’s Stratix 10 FPGA.

DARPAs Andreas Olofsson, manager of DARPA’s CHIPS program, reitterated the need for a standard communications interface. “… we need a plug-and-play standard……once we have that standard, you can imagine vendors offering a number of chiplets for sale.” The CHIPS program community is in the process of accepting the Intel AIB technology for this purpose.

USATF Jr Olympics

For my faithful readers of IFTLE, a quick update on the running career of grandaughter Hannah. In July of 2017, we discussed her new found ability to run on an elite level [link].

Well…she has continued this pursuit both with her Jr High and track club “Track Houston” and this year made the Jr Olympics. That’s right, I can now say that she is officially considered one of the fastest 13-14 yr old girls in the USA. She ran in the 4×400 and 4×800 races and medaled in the 4×800 as shown below.

For all the latest on advanced packaging, stay linked to IFTLE…


IFTLE 391 DoD Worried About Access to State-of-the-art Packaging Technologies

By Dr. Phil Garrou, Contributing Editor

Continuing last week’s conversation about access to state-of-the-art packaging capabilities if you are not a large volume player, let’s look at the current concerns of the USG (US govt).

In the early years of the microelectronics industry the US Govt with its defense and communications requirements drove the electronics industry. In recent decades, however, commercial applications and high-volume production have dwarfed US Govt demand, resulting in commercial market forces driving the industry. Advanced packaging in the 1980s – 1990’s was driven by the integrated  device manufacturers (IDMs) in the US and Japan ( IBM, AT&T, TI, Motorola, DEC, HP, Hitachi, Fujitsu, Toshiba, NEC).

By the early 2000’s it had become clear that the demand for more and more I/O required a move to area array interconnection to replace the I/O limited Wire Bond technology that was in place. Up till then area array technology, exemplified most prominently by “bumping” was a technology only practiced by the mainframe computer companies. Starting ~ 2000  several of the evolving assembly houses in Taiwan and Korea like ASE, Amkor, Siliconware, STATSChipPAC (all located in Asia) licensed the US bumping and wafer level packaging technology of FCT (Flip Chip Technologies, Phoenix ,AZ) and Unitive Electronics (RTP, NC) and made such technology available worldwide. This technology was quickly adopted into portable consumer as well as computer products.

The massive commercial bumping capacity that was put in place in Taiwan and Korea delivered higher profit margins to these assembly companies separating them from those without such technology availability, and making US companies reliant on getting such technology from overseas. It also made it clear to these select assembly companies that “advanced” packaging was a higher profit margin packaging and assembly business that was worth their investment.

During the period 2000 – 2015 we slowly saw a year–to-year migration of the leadership in advanced packaging technologies moving from the afore mentioned IDM’s to these select major assembly houses in Asia.  This shift is best seen by analyzing the presentations at the IEEE Electronic Component Technology Conference (ECTC) which is the accepted world showcase for advanced packaging technologies. Ironically, the assembly houses, which were created to absorb the “packaging grunt work” the IDMs no longer wanted to do, discovered the potential financial advantage of developing the next generation advanced packaging solutions and ran with it.

We now appear to be in the process (2015–2020) of shifting leadership to the large global foundry houses like TSMC, Samsung and GlobalFoundries. Their ability to obtain finer geometry features using front end technologies, their comfort with processes like CMP and their comfort working in clean environments has put them in a position of strength for the latest high density packaging solutions.

Obtaining business with the Apple’s of the world now hinges on having both the best chip solution and the best packaging solution. Companies like TSMC saw this early on and have been investing heavily in developing the latest leading edge packaging solutions

Trusted Microelectronics Joint Working Group

In 2017 a diverse group of semiconductor industry, defense primes, DoD, and research institute professionals was assembled as a Joint Working Group to look into the future of microelectronics in the US and specifically how that future will impact the economic well-being and defense of our country. That list of participants is shown below:

Their findings included:

– there has been a migration of key supply chain elements particularly chip fabrication and packaging to overseas locations

simple access to the parts needed from the larger global electronics industry base has become a  large concern

The figure below was developed to show the tactical and strategic nature of the access issue.

When looking at emerging technologies they especially called out:

1. 3D / Heterogeneous Integration

2. Compound Semiconductor

3. Advanced Node CMOS

4. Other Novel Technologies: Advanced Digital, Analog Computing, Neuromorphic and Quantum

Access to Adv Node CMOS

The DoD requires access to state-of-the-art (deep node) CMOS for a number of current applications as well as R&D efforts for future systems. Advanced digital computation requirements benefit tremendously from state-of-the-art (SOTA) CMOS solutions.

SOTA CMOS fabs are very large and expensive with high volume commercial facilities costing over $10B. R&D expenses are also enormous. For this reason, there are only 4 companies left that offer SOTA CMOS: INTEL, GLOBALFOUNDRIES, Samsung and TSMC. All of these companies rely on the scale of high volume manufacturing to finance the capital and R&D requirements to maintain their competitiveness.

As a result of the enormous cost and complexity of the SOTA CMOS business, DoD access has become very difficult in recent years. There is a substantial difference in business model between commercial needs to produce very large volumes of a small mix of parts while DoD requires substantially fewer parts across a broad device mix. The NRE costs associated with SOTA design and fabrication make the high mix, low volume requirements difficult to attract commercial interest in servicing the DoD.

DoD has addressed this challenge in the past through its “Trusted Foundry” contract with IBM. This ended in 2015 with the sale of IBM Microelectronics to GlobalFoundries (GF), a foreign owned firm. The

In the long run, it is important for DoD to have assured access to secure SOTA CMOS from a variety of sources. Given the very different business models of the commercial world and DoD, this will be a challenging goal to achieve.

Access to 3D / Heterogeneous Integration technology

In terms of advanced packaging this study specifically called out  3D / heterogeneous integration technology and the assembly of microbumped flip chip dies onto interposer substrates and noted that :

“…..Therefore, the challenge for trusted heterogeneous integration technology is to stand up and maintain trusted 2.5D / 3D integration and assembly supply chain capabilities”

They concluded that :

There is grave concern today about the growing gap between commercial suppliers (many critical suppliers are offshore or owned by foreign entities) and defense needs. In the past, semiconductors and even software were created from a small number of large onshore vertically-integrated companies that had close ties and large business interests with the defense industries. The disaggregation of this industry into hundreds of international suppliers combined with commercial uses/volumes of microelectronics that far outstrip the DoD needs has created this alarming gap. This gap continues to grow.” 

“A National Strategy will need to encompass the entire lifecycle of DoD system needs (up to 50 year lifetimes and small volumes) and mesh that with the relative “mayflies” of the commercial world (< 2 years lifetimes and billions of devices…..The existence of China’s National Semiconductor Strategy cannot go unmentioned. They aim for total self-sufficiency and are investing heavily in their infrastructure. The US should not blindly emulate this approach but needs to develop its own unique strategy for ensuring long term access to secure components as well as enabling US economic vitality in this area. Creation of a practical US National Microelectronics Strategy will be a challenging multi-year process, requiring good insights into the future of the industry as well as intimate knowledge of the workings of the USG. The authors of this paper believe that this process should start now.”

Assured Supply for Microelectronics Manufacturing:Solicitation Number: W15QKN-18-X-02S7

In June 2018  the U.S. Army Emerging Technologies Contracting Center, on behalf of the Under Secretary of Defense for Res and Eng, issued a request for information (RFI) seeking information on business models and/or public-private partnerships (PPP) to provide long-term, economically-viable, assured sources to meet US commercial and government needs for state-of-the-art (SOTA) microelectronics design, fabrication, and packaging within the US domestic ecosystem. The U.S. Government (USG) is seeking inputs from the commercial microelectronics industry, industrial and standards groups, research and development contributors from government and industry, and states and regional governments, and private capital market players in this area. “This is a RFI not a Request for Proposal (RFP) or a promise to issue an RFP in the future”.

They define the problem as “The licit and illicit offshoring of intellectual property (IP), research and development (R&D), and production capabilities threaten the ability of U.S. companies to capitalize for the market-driving technologies of the future, opens critical infrastructure and data systems to attack, and degrades our national security. The current set of incentives offered by the USG can be better aligned to retain domestic capacity and technology leadership. The USG only represents less than 2% of the global commercial market for  microelectronics, and with current USG unique procurement policies, standards, and security requirements, industry lacks incentives to willingly and affordably meet the government microelectronics demands.”

Other nations will innovate faster, capture market share, and obtain the best technology at the expense of the U.S., impacting domestic innovation and the manufacturing base. The U.S. may lose the ability to realize the best ideas and capabilities across commercial and national security sectors, becoming dependent on competitor nations. A reliance on foreign made microelectronics with unreliable assurance and security could disrupt USG access to advanced technology critical to national security, and in general, devastate U.S. manufacturing, business, financial, and communications infrastructure.”

The goal of the information procurement is to develop a program to “…ensure the U.S. is recognized globally as the preferred source for superior microelectronics; delivering technology faster, more efficiently, and with the highest levels of assurance. …. Domestic foundries and packaging capabilities will support these activities, translating leading-edge R&D into new products. Assurance and security become competitive advantages for U.S. industry practiced at all stages of development and production ensuring the nation delivers reliable and superior microelectronics components, systems, and capabilities more quickly than other nations.”

The Government recognizes the need to proactively engage with industry to make such efforts successful . They report that they are executing a plan to provide semiconductor and microelectronics leadership now and into the future with a “whole-of-government effort”.  The U.S. Army Emerging Technologies Contracting Centeris requesting information on behalf of the USG on how to achieve the above outcomes most effectively.

Sources are encouraged to provide their ideas for the structure and sustainability of commercial business arrangements and/or PPPs necessary to deliver microelectronics manufacturing and leadership in a domestic ecosystem now and into the future. Sources are requested to respond to this RFI with a white paper.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 390 Raytek – An Accessible Wafer Level Packaging Start-up in Taiwan

By Dr. Phil Garrou, Contributing Editor

While all readers of IFTLE know that advances in chip packaging have been proceeding at a rapid rate at the same time as front end IC advances are becoming harder and harder to achieve, access to these advanced technologies are difficult if you are not one of the large volume players. So, if you are a low volume supplier to the DoD or a custom supplier to smaller companies with low volume requirements you will have trouble finding someone willing and capable of doing business with you in advanced packaging and interconnect.   Note, I’m not talking about accessing 3DIC with TSV, I’m talking wafer level packaging including bumping, RDL, copper pillar bump etc. Try going to Amkor, ASE, TSMC or Global Foundries if you need a 100 wafer or 25 wafer order filled.

The response you get will be “No, thanks…nothing personal, you understand… it’s just a business decision.”

Now some of you may say “wait a minute…I know that Xilinx does 2.5D for FPGAs at TSMC and those are low volume products”…You are correct…but that’s for Xilinx…and the rest of you are not Xilinx.

Lets take a break from ECTC coverage to look at an under the radar advanced packaging option if your volumes don’t allow you to access the top tier foundries and assembly houses.

Raytek Semiconductor

Raytek Semiconductor was formed in April 2016 in Hsinchu Taiwan by packaging  veterans Johnson Tai  and Dyi Chung (DC) Hu to service customers’ needs specifically in wafer level packaging. Raytek is tooled for  both 300 and 200mm wafers. Beside silicon , their line can also process glass and  ceramic  wafers. Raytek also have a separate 150/100mm manufacture line to process GaN and other non silicon wafers.

Current clean room space is 1677 sq meters with phase 2 additional space of 1582 sq meters coming on line  as required. Process areas are class 100. Current wafer capacity is 12,000 wafers/mo.

Since setting up the company two years ago, they claim ca. 100 customers  products have been designed with a 100% passing rate after function evaluation and reliability test.

Raytek WLP services include:

– RDL: Cu RDL & Cu/Ni/Au RDL

– Bump: Cu Pillar Bump & Lead Free Bump

– WLCSP: Plated Bump

– WLCSP: Ball Drop (Q4/2018)

300mm Services:

– Cu/Ni/Au RDL, Thick Cu UBM/RDL

– Cu/Ni/Au RDL for Au or Cu wire bonding

– RDL L/S = 5/5um and Multi-layers RDL (up to 4PI/3Metal)

– Cu RDL for GaN wafers

-Low or high temperature cure dielectrics can be selected depending on requirements, 4-10um std.

-Applied in specialty memory , high power IC

– Bump ( Lead free bump, Cu pillar bump )

– Lead free solder and low alpha emission lead free solder can be plated

– Copper pillar pitch is 40µm, with max height 135um

-Applied in ASIC, Controller, Power, RFIC, High end memory devices (8GDDR4,HBM)

– One Stop Service

– Backside Grinding, Backside Metal, Dicing, Tape & Reel done in house

So, if you’re in need of these types of services check out Raytek.

So for all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 389 Samsung 2μm L/S Panel Level Packaging Technology Revealed at ECTC

By Dr. Phil Garrou, Contributing Editor

This week and next, IFTLE will take a look at the key Samsung presentations from the recent ECTC meeting in San Diego.

As we have said many times on IFTLE, fine pitch solutions is certainly an area where the major foundries have a packaging advantage over the OSATS. The Samsung Packaging Development Team presented a paper entitled “Fan Out Panel Level Package with Fine Pitch Pattern” discussing the technical challenges of fine pitch processing on a panel level process.

Samsung Panel Level Processing

Panel level package (PLP) is being examined because it appears to be the most cost-effective technology due to its large working area. Compared with 300mm wafer size, about 3 times number of units can be accommodated in Panel of 500 X 400 mm size. SEMCO (Samsung Electro-Mechanics) has developed a platform for FOPLP as shown in the fig below.  RDL technology enables the IO’s from semiconductors fanned out through RDL to PCB, while organic PCB is introduced as core structure in Fan-out area.

Many concerns remain regarding commercialization of Panel Level Packages related to process capabilities and yields. The most emphasized ones concern warpage and the generation of fine features. As we know, Fan out can be done RDL last or RDL first. As requirements of finer patterns are needed, RDL first process is seriously considered because fine patterns can be easily obtained on relatively flat carriers compared with molded wafers or panels. Samsung points out that currently patterns of about 10/10 um line and space has been successfully formed in chip first Fan-out package and 5/5 um of pattern is expected to happen in advanced Fan-out package, while 2/2 um of pattern required for die to die interconnection in such applications as 2.5D interposer drive the consideration of an RDL first processes solution.

In this study Samsung attempted to fabricate 2/2 L/S on glass and PWB panels of 415mm x 510mm size. The CTE of organic carrier composed of resin with glass was 8 ppm/C and the thickness was 0.6mm. The CTE of the glass carrier was also 8ppm/C and the thickness was 1.1mm. The Fig below compares organic carriers and glass carriers with regard to the extent of panel warpage.

The warpage of the glass panels was less than a quarter that of organic carrier. In addition, during the assembly process of large die with fine pitch micro bumps (typically 55um pitch) also requires very flat condition to avoid warpage caused non-wets or shorts.

Samsung feels that the concern that 2/2 um patterning on panels will be difficult may be due to the observed panel warpage and flatness. As the pattern pitch is decreased, available depth of focus (DOF) during lithography must be reduced, which requires very flat conditions. As the pattern pitch is reduced below 2/2 um, available DOF is decreased below 10um and toward about 5um level even though it depends on exposure equipment. Therefore, large panel warpage or high waviness on surface to be exposed may cause poor capability or yield with fine pitch.

Using the glass panels the Samsung group was able to do photolith and produce 2/2um L/S as shown in the fig below. A PBO dielectric was used to create 2 layers of 2/2 interconnect with 6um vias connecting them.

So a rigid carrier with high thickness or stiffness seems to be needed because multi layers on organic carrier resulted in the failure in exposing equipment (stepper) due to the high panel warpage. In case of glass carrier, about 5mm warpage was observed on the panel.  Even in that condition, the stepper table could hold the panel effectively under vacuum and there was no problem related with focusing the panel surface.

Another consideration regarding multi-layered panel was whether the pattern below passivation may affect the flatness of the passivation layer surface which consequently affects the fine pattern on it (i.e. is he surface planarized enough so that CMP or some other form or planarization aren’t needed between each layer of interconnect) . In the cross-sectioned image of 2/2 um pattern on second passivation layer shown below you can see the dip in the central area, which contained no sub layer features. Further study is needed to determine how much is flatness degradation due to lack of global planarization will induce failure in 2/2um pattern above.

Samsung also presented an excellent discussion on known good substrates.  In case of chip last RDL first process, the dies must be bonded to known good RDL. Therefore electrical test of the RDL carrier is a very important issue. One has to deal with the small bump pad size of about 20 – 25um diameter and the extremely large number of bumps (about 200K). A major issue is the probing of the interconnect. It is difficult because the electrical probe cannot be contacted on both side of all signal lines, but some must be checked by contacting on only one side of the signal lines. To check by only one side contact and decide if there is open or short, the capacitance of line or pattern must be measured exactly. Feasibility tests were done for one side contacted electrical test. The intentionally opened lines are well distinguished from the good signal lines as the line opened at the farthest position is differed by about 40% of measured values.

This is technology obviously still in R&D, but it is the strongest set of data that IFTLE has seen showing the possibility of manufacturing high density interconnect on large panel format…It certainly showed Samsung flexing it’s technical muscle !

For all the latest on Advanced Packaging, stay linked to IFTLE…