Insights From Leading Edge

Monthly Archives: August 2018

IFTLE 395: And Then There Were 3; IC History for the Younger Generation

By Dr. Phil Garrou, Contributing Editor

The IC industry “poker championship” is down to the last table

The IC industry started out like a poker championship tournament. Hundreds of players, through the years, put up their entry fee to compete ( i.e. paying for their fabs) and the competition began. The most money was always made at the advanced nodes, i.e. the leading edge. There were winners and losers through the decades and we are finally down to the last table of players TSMC, Samsung, GlobalFoundries and Intel.

Last week, GlobalFoundries (GF) CEO Tom Caulfield announced that GF is putting its 7nm FinFET program on hold indefinitely and restructuring its research and development teams to support “…its enhanced portfolio initiatives”. The company will shift development resources to focus on its 14/12nm FinFET platform, “…delivering a range of innovative IP and features including RF, embedded memory, low power and more”. To support this transition, GF will initiate a ~ 5% global workforce reduction, however a significant number of top technologists will reportedly be redeployed on the 14/12nm FinFET programs [link].

Gary Patton, GF’s CTO added “…the number of players going into these advanced nodes has dropped significantly as result of the dramatic increasing costs to design in these leading-edge technologies… … then you look at the R&D cost …the R&D cost of these leading-edge nodes has been going up exponentially”

If you’re a long time reader of IFTLE, you already knew that!

On the heels of this announcement, AMD has announced that they will move all of its 7nm production on both CPUs and GPUs to TSMC [link]

Intel who launched their 14nm process in 2014 initially forecast their 10nm process for late 2016. Then that schedule slipped back to 2018. Now it’s slipped back into late 2019. These “Cannon Lake” delays are widely reported due to yield issues. [link]

Not good news for Intel when added to reports from Bloomberg that  Apple will start using their own chips in their products starting ~ 2020 (program code name “Kalamata”)[link]. Apple reportedly produces 5% of Intels income.

As we have been saying in IFTLE for many years now, the front end, node to node march called Moore’s Law is not dead, but certainly has been marginalized to the point where only a select few with major $$ and volume applications can play. For the rest of us, packaging is the new game in town and you better start learning the options that you have there.

A History Lesson for the Younger Crowd

Seeing all the global 20 somethings attending conferences like the ECTC is stimulating because it means our industry will continue to have a bright future. Talking to them reminds me that every now and then they need a history lesson so they can understand where all this came from.

I found the following schematic of the origins of our industry in a 1997 business week article. So if you have ever said “Who is Fairchild” and why does anyone care about them…here is the answer. As you can see some were winners and some were not.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 394 DoDs ERI will Depend on Sky Water; Will Apple Get Caught in the Trade War?

By Dr. Phil Garrou, Contributing Editor

More on DARPAs Electronics Resurgence Initiative

In IFTLE 392, we discussed DARPA’s Electronics Resurgence Initiative (ERI), a $1.5B 5 year effort to remake the U.S. electronics industry. [link]

An interesting article appeared in this month’s IEEE Spectrum magazine entitled, “The Foundry at the Heart of DARPA’s Plan to Let Old Fabs Beat New Ones” [link]

Among the 42 projects listed in the ERI, the “Revolutionizing Computing Systems through Dense and Fine-Grained Monolithic 3D Integration” project at $61MM is the largest on the list. Its goal is to use monolithic 3D integration to make chips made using decades-old fabrication processes competitive with chips made using today’s bleeding-edge technologies. The project is based on technology that allows carbon nanotube transistors and resistive RAM memory to be built on top of ordinary CMOS logic chips. It was developed by Max Shulaker, of MIT, and his colleagues at Stanford University. The program is being scaled up at SkyWater Technology Foundry in MN.

Over the next three years, Shulaker’s group at MIT will focus on developing a manufacturable process, and the Stanford group will create design tools that will help engineers take advantage of the increased performance that the stacking of CMOS, nanotube transistors, and RRAM offers. Skywater will develop and test a high-yield “process flow” that works in its foundry. So exactly who is SkyWater technologies ?

In March of 2017, Cypress Semiconductor sold its 200mm Fab 4 in Bloomington, Minnesota, to SkyWater Technology Foundry for $30 million [link].

Skywater announced that their intent was to operate the fab as a stand-alone USA specialized foundry. Skywater agreed to manufacture wafers for Cypress under a multi-year supply agreement while it tries to attract other foundry customers (similar to the IBM Global Foundry agreement of a few years ago). Cypress had operated the automotive-qualified fab since it acquired it from Control Data VTC in 1990. The fab reportedly has a clean room floor space of 80,000 square feet and was capable of 16,700 wafer starts per month. Cypress had about 450 employees at the Bloomington wafer fab in December 2015. ” SkyWater reports that it supports both low volume, fast turnaround processing and high volume production. It runs manufacturing processes from 0.35-micron down to 90nm.

The SkyWater facility maintained its “trusted site” accreditation allowing it to provide wafer fabrication, design, wafer test, and broker services to the US government as a trusted supplier. SkyWater announced its plans to expand engagements with the DoD [link]

According to Sky Water, they are now the only American-owned pure-play silicon foundry in the country as shown in the fig below.

The Sky Water technology roadmap is shown below.

Could Apple could find itself at the center of the US vs China trade war?

This from China’s Global Times [GT]  [link] “…. Why has the California-based company (Apple) enjoyed remarkable success in China, while some Chinese companies have experienced big losses amid a growing trade conflict with Washington …”

Apple recently reported financial results for its fiscal third quarter and sales to the greater China region gained 19 percent to $9.6 billion. GT contends the company’s better-than-expected quarterly result in China was a major reason for the surge in its shares. China serves as a key production and processing base for Apple. Many Chinese companies have been included in Apple’s production chain to provide parts and components or assembly work.

GT contends that the Apple success in the Chinese market “…may provoke nationalist sentiment if US President Donald Trump’s recently adopted protectionist measures hit Chinese companies hard”.

China is reportedly the most important overseas market for the Apple, leaving it exposed if Chinese people make it a target of anger and nationalist sentiment. China reportedly doesn’t want to close its doors to Apple despite the trade conflict, but GT warns “.. if the US company wants to earn good money in China, its needs to share its development dividends with the Chinese people..” and  “It is impractical and unreasonable to kick the company out of China, but if Apple wants to continue raking in enormous profits from the Chinese markets amid trade tensions, the company needs to do more to share the economic cake with local Chinese people”.

GT notes that “Apple’s contribution to job creation in China is notable, but the company enjoys most of the profits created from its Chinese business”. In the case of the iPhone, their statistics show Chinese processors only get 1.8 percent of the total profits created by the device.

For all the latest in advanced packaging, stay linked to IFTLE…

Readers –

We have received the following message from Bruce Gray CEO of TSI Semi challenging the information presented by Sky Water on their slides that I presented above.

“The information from Skywater included in this SST article …[IFTLE 394]…regarding TSI Semiconductors Corp. is completely inaccurate.   TSI Semiconductors Corp is 100% U.S. owned by U.S. citizens and not as the map by Skywater indicates.   The subsequent statement by Skywater that they are the only American owned, pure play Silicon foundry is therefore wrong as well.

TSI Semiconductors Corp is ITAR and Trusted foundry certified and has numerous customers that use our high quality and fast cycle time manufacturing for their critical projects.   TSI provides MEMS, Superconducting, and Photonics process development and manufacturing services, and, TSI serves the rapidly expanding medical device and analytical “lab on a chip” product markets also.

Importantly, TSI Semiconductors is certified to the new Automotive IATF-16949 manufacturing standard.  Our facility has 150,000 sq ft of clean room with a maximum capacity of 25,000 200mm wafers per month and lithography capability as small as 110nm.”

IFTLE looks forward to doing a blog on TSI in the near future…

IFTLE 393 Samsung Adv Pkging at ECTC: Emphasis on Warpage Control

By Dr. Phil Garrou, Contributing Editor

At the 2018 ECTC, Samsung presented several papers on their advanced packaging activities.

Samsung teamed with SUNY Binghamton to discuss “design Guidelines of 2.5D Package with Emphasis on Warpage Control and Thermal Management.” A 2.5D Package is composed of many material sets and in general its size is larger than conventional single chip packages. The CTE of substrate is a well-known factor to control warpage in a single die packages. However, the existence of another layer (interposer) makes the problem more complicated. Optimization of the material sets, which include lid, EMC, chip, Interposer and geometric factors, are essential.

From their modeling studies it is clear that substrate CTE is more influential than other criteria.

They developed the following guideline for warpage control and thermal management:

Area ratio of lid attach, lid thickness, EMC CTE and substrate CTE are major factors influencing for warpage. For thermal management, EMC coverage on top of the chip, (cooling) fan speed, and conductivity of TIM are the major factors that affect thermal resistance.

In their presentation on “Low Cost Si-less RDL Interposer Pkg for High Performance Computing Applications” In this presentation a concept for a Si-less redistribution layer is descried for server/HPC applications and warpage behavior, electrical performance and reliability of the RDL interposer package were evaluated.

Si-interposer have attracted attention for high end sever products due to  high electrical performance at low power consumption. The key barrier of Si-interposer adoption, utilizing TSV, is high manufacturing cost for large interposer sizes. They suggest a Si-less redistribution layer (RDL) interposer platform for high performance applications as a low cost package solution.

The table below compares 2.5D Si interposer technology to wafer level and panel level RDL interposers.

The fabrication process flow of RDL interposer package is classified into six main steps as summarized in the fig below.  RDL formation, multi-chip bonding on RDL, encapsulation, chip exposure, solder ball attachment, and interposer assembly on PCB. The most challenging aspect of the assembly is reportedly the warpage control of interposer packages, due to the large size and multichips.

Samsung clams that the RDL interposer package has the advantage of lower manufacturing cost over Si-interposer by replacing TSV with RDL. Their results showed that RDL interposer warpage is more controllable than Si-interposer at room and high temperature by the optimization of design, process condition and material selection. Their test structure, a RDL interposer package whose size is larger than 3000mm2 included four HBMs and one ASIC chip, was successfully fabricated and they determined that the electrical loss of RDL interposer was lower than Si interposer case. Mechanical simulation showed RDL interposer reduced joint stress by 34% compared to Si interposer. They predict that RDL interposer tech will become one of the most promising solutions for low cost and large size packages in the near future if “….fine patterning technology is developed below L/S 2/2um.

For all the latest in advanced packaging, stay linked to IFTLE…