Insights From Leading Edge

Monthly Archives: September 2014

IFTLE 210 IBM Global Foundries reaching closure?; Semicon Taiwan 2014 part 1: Hitachi Chem & SPIL

IBM / GlobalFoundries – On Again ??

When last we discussed the soap opera that is called the IBM Global Foundries negotiations, I confirmed that IBM was actually paying for GF to take the semiconductor operation (which has been losing ~ $2B/yr) off their hands.

Since then the media had announced that the deal was off. But this made no sense, IBM had gone to far and their Semi employees would be leaving on their own since this was no longer a site to develop a semiconductor manufacturing career. Indeed GF began hiring IBM employees.

On 9/19, the Poughkeepsie Journal reported that “a source involved in the negotiations” indicates that “they are headed to arbitration as early as next week in the latest effort to strike a deal for IBM to sell its semiconductor manufacturing operations.”

SEMICON Taiwan 2014

SEMICON Taiwan is always a gathering that produces Major packaging announcements.

The Advanced Packaging Technology Symp was chaired by C. S. Hsiao, Vice President, Engineering Center, SPIL.

The SiP Global Summit and 3D Technology Forum was chaired by CP Hung VP of corporate R&D for ASE and DC Hu Sr VP of R&D and new business development for Unimicron.

CP Hung DC Hu


Hitachi Chemical

Toba of Hitachi Chemical described their embedding insulation sheet (EBIS) for FOWLP and FCCSP. The process flow for FO WLP is shown below using PBO ( HD 8940 ) as the RDL dielectric.

hitachi Chem 1


Proper  EBIS CTE and modulus and/or  die thickness was shown to reduce warpage by as much as 60%.

EBIS was also used for FC CSP packaging:

hitachi Chem 3


Using EBIS as a laminated MUF replacement (mold and underfill) resulted in center voids in the package. Compression molding was necessary to achieve void free structures.


M Lu of SPIL addressed “The Next Wave of 2.5D Applications”.

As IFTLE has stated in the past, the composition of future interposers will depend on the density requirements of the applications. Right now the only technology available to satisfy “G1” requirements is silicon substrate technology.



SPIL has optimized the following processes in order to be able to address this market space.

spil 2


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…


IFTLE 209 Samsung announces TSV based DDR4; What is Intel eMIB?; Amkor says the wait for 3DIC is not over yet

By Dr. Phil Garrou, Contributing Editor

Samsung finally announces commercialization of TSV based DDR4

IFTLE has been reporting for awhile that a Samsung announcement of stacked memory based on TSV technology was imminent. [ see IFTLE 123 “Intels Bohr on 3DIC;Samsung DDR4 roadmap…” especially since similar announcements have already come from Micron and Hynix.]

On Aug 26, Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Samsung has started operating a new manufacturing line dedicated to TSV packaging, for mass producing the new server modules. The new RDIMMs include 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. The low-power chips are manufactured using Samsung’s most advanced 20-nanometer (nm) class* process technology and 3D TSV package technology.

The new 64GB TSV module reportedly performs twice as fast as a 64GB module that uses wire bonding packaging, while consuming approximately half the power.

Samsung believes that in the future it will create even higher density DRAM modules by stacking more than four DDR4 dies using 3D TSV technology.

Samsung has been working on improving its 3D TSV technology since it developed 40nm 8GB DRAM RDIMMs in 2010 [see IFTLE 65, “Samsung’s 32GB RDIMM DDR3…” ], and 30nm 32GB DRAM RDIMMs in 2011 using 3D TSV.

Fig 1

Amkor’s Liang says 3DIC will take another 3 yrs to get to HVM

At a press event held prior to the official opening of Semicon Taiwan 2014, Mike Liang, president of Amkor Technology Taiwan, announced that “demand of 3D ICs may take another 3 years due to concerns of high production costs.” He added that “…at present, only a few specific applications that require extremely high performance ICs require the use of 3D ICs, but the amount of such 3D ICs is not sufficient enough to support a full production line.” I’m sure this served to pour cold water on the subsequent 3DIC tech forum!

Intel Announces Embedded Multi die Interconnect (EMIB)

Intel recently announced that a new technology “Embedded Multi-die Interconnect Bridge” or EMIB will be available to 14nm foundry customers [link].

They claim it is a “… lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” While neither Intel nor any initial press reports gave any indication of exactly what this means.

It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014 [link].

In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below:

Bridge Interconnect as described in recent Intel patent.

Bridge Interconnect as described in recent Intel patent.

A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.

While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.

Since the 2.5D interposer has been reduced in size to the interconnect bridges, this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D

Intel EMIB Module in Cross Section

Intel EMIB Module in Cross Section

While Intel released the following description: “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed,” IFTLE thinks this is somewhat misleading.

The packaging analogy to what they have done is as follows:

A high density bumped chip could be put down on to a high density build up PWB,  but in most cases the high density bumped chip is placed on a smaller BGA substrate which is then put onto a lower density, lower cost PWB.  The latter is the lower cost solution. In this case, large expensive high density interposers are avoided, and the much smaller emib are used for the high density interconnect. It will be interesting to see what if any the cost differential will be here.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 208 ECTC part 3: Thermal Compression Bonding – STATS, Toray, Qualcomm

By Dr. Phil Garrou, Contributing Editor 

SCP Status

Before we continue our look at key papers from the 2014 IEEE ECTC Conference, the latest on the potential sale of STATSChipPAC (SCP). In June SCP, announced  that it ended talks with one party (thought to be ASE) while discussions with other potential bidders were continuing.

Bloomberg now reports that the Chinese chip-testing companies Jiangsu Changjiang Electronics Technology and Tianshui Huatian Technology are considering bids for SCP and that a deal for SCP, valued at ~ $ 1B could be reached early next month.  [link].

Semiconductors have been labeled a  “strategic industry needed for China’s economic development and national security” by the Chinese Govt. China announced increased financial support for the industry and plans to set up a national investment fund according to Bloomberg.

Continuing our look at key papers from the 2014 IEEE ECTC conference

Thermo-compression Bonding

The advent of 2.5 and 3DIC has caused revisions in the way area array bump interconnect is carried out. The packaging hierarchy has traditionally been for BGA balls (~ 500um) to connect packages t boards and for C4 bumps (100-150um) to connect chips to packages.

Chip stacking with requirements for tighter pitch would prefer to have copper to copper connection, but such thermo-compression bonding currently requires 350-400C, 200kPa and most importantly 30+ minutes which makes high volume manufacturing impractical. Therefore the industry has adopted the   micro-bump and the copper pillar bump for such mating.

Sematech has put out the following cartoon to show approximately when technologies have to be changed based on required pitch.



Most OSAT roadmaps show that standard solder reflow can be used down to ~ 40um after which compression bonding must be used to avoid shorting.



A closer look at these mucro bumps (see below) usually reveals a Ni barrier layer on a copper pillar capped with Sn/Ag solder.



Such fine pitch connections make it difficult to underfill and have driven the refinement of pre applied underfills [both film (called non conductive film, NCF) and paste (called non conductive paste, NCP) ]. These technologies only work when one has good manufacturing control over both solder reflow and underfill cure.

Let’s look at some issues concerning such interconnect that came up during ECTC 2014.


Y. Jeong detailed the “Optimization of Compression Bonding Processing Temperature for fine pitch copper column devices.”     They examined thermal compression with non-conductive paste which they call TCNCP. The heat transfer from heating source to bumps must be tightly controlled in order to achieve the optimized bump temperature for the purposes of melting and soldering. To minimize voiding issues such as air entraps, a very short time window for curing has to be used in the NCP process. They determined the key parameters as shown below.



They concluded that “to have a successful bond, one of the most important keys is to obtain an optimized temperature profile which considers the ramp up/down speeds and times. The ramp up/down speeds and times affects the NCP flow behavior, void creation, and residual stress of the final product. In this regard, the peak and dwell time shall be precisely controlled to provide enough time for melting and soldering of bumps with substrate pads.”


Y. Liu of Qualcomm examined “Filler entrapment and solder extrusion in 3DIC Thermo-compression uBumps.”  Qualcomm indicates that filler entrapment could negatively impact electromigration in the solder joint.

The main reason for filler entrapment is reported to be premature cure of the pre-applied underfill caused by not fully optimized process condition and/or bump geometry. Once curing initiates, solder wetting is no longer able to push out filler and underfill from the joint due to the increased viscosity of underfill.

They also find solder extrusion from the side of the ubumps and conclude through examination of large arrays of bumps that the extrusion appears to be random.




T. Nonaka of Toray described “High Throughput thermal compression NCF Bonding.”  Torray points out that thermo compression bonding suffers from throughput issues because of the process flow shown below which requires the bonding head to cool between chip placements.



They propose a logical process change where the die are all placed and then cured and reflowed at once (gang bonded) as shown below.



For all the latest in 2.5/3DIC and advanced packaging, stay linked to IFTLE…

IFTLE 207 IEEE ECTC part 2: Advances in Fan-out Packaging

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the “Fan Out” papers that were presented at the 2014 ECTC.

STATSChipPAC (SCP) and the totally encapsulated WLP

Tom Strothman from SCP presented an update on their fan-out technology to produce fully encapsulated WLPs. Strothman reminded us that the WLP was invented, patented and commercialized by Flip Chip Technologies (FCT) in 1998 when they released the “Ultra CSP”. Tom was part of that FCT team along with Pete Elenius.  I recall that well, since I was at Dow Chemical in those days working with FCT on the program with my team which included current industry veterans Boyd Rogers and Andy Strandjord.

Luu Nguyen, then at National Semi, and a licensee of the FCT technology  was the first to coat the backside of the WLP with a layer of molding compound both for protection and to enable laser marking.

SCP has now taken this to the next level by developing their eWLCS (an acronym I assume for Wafer Level Chip Scale)  which is the only WLP to offer protection on all sides of the package.

The process starts with a high volume manufacturing flow developed by STATS ChipPAC for fan-out products. In this manufacturing method the wafer is diced at the start of the process and then reconstituted into a standardized wafer (or panel) shape for the subsequent  process steps. The basic process flow for creating the reconstituted wafer is shown below. The singulated die are accurately placed face down onto the carrier with a pick and place tool. A compression molding process is used to encapsulate the die with mold compound while the active face of the die is protected. After curing the mold compound, the carrier and adhesive foil are removed in a de-bonding process resulting in a reconstituted wafer where the mold compound encapsulates all exposed silicon die surfaces.

After the reconstitution process, the reconstituted wafer is processed with conventional wafer level packaging techniques for the application and patterning of dielectric layers, thin film metals for redistribution and under bump metal, and solder bumps. In the final dicing operation a thin layer of mold compound, typically < 70um, is left on the side of the die as a protective layer as shown below.


One would assume that the process flow shown above would have higher cost since there are additional steps required for reconstitution at the start of the flow. SCP contends that there are two key factors that offset the cost of the additional steps. 1) In the case of the 300mm reconstituted panel used here the cost is very competitive for silicon wafers with a diameter of 200mm and below. SCP claims the cost of processing a 300mm reconstituted panel is approximately 1.7x the cost of processing a 200mm silicon wafer in WLCSP, however the units per panel (wafer) increases by a factor of 2.3x, effectively offsetting the cost of reconstitution. 2) Since known good die can be selected at the start of the process, advanced devices that have a lower electrical yield can be tested in wafer form prior to the process. If the incoming wafer has a probe yield of 85%, then 15% more units per reconstituted panel can be processed to offset the cost of the reconstitution process.

Since the reconstituted panel size is no longer linked to the incoming silicon wafers size, the panel size can be increased over time and provide further cost reduction.

Because of the presence of molding compound, the RDL on these structures cannot use the typical PI, BCB or PBO dielectrics, but rather must use a as yet unnamed low temp cure material.

TCT (thermal cycle tsting) passes 500 cycles ( -4o to 125 C) and drop testing passes the JEDEC 30 drop requirement.

Siliconware (SPIL) panel fan-out packaging (P-FO)

Chang of SPIL discussed their efforts to commercialize he panel fan-out package concept  by combining  PCB, semiconductor back-end, semiconductor WLP and LCD Gen 2.5 glass processing technologies. This effort requires high accuracy die bonding and die shift compensation at film lamination, lower warpage sheet form film lamination, good copper trace plating uniformity control at large panel area and also precise photolithographic technique.

Known good die are reconstructed on the LCD Gen 2.5 (370X470mm) size glass carrier with adhesive temporary bonding material.

Processing issues are identified as warpage, die shift “coordinates compensation at lithography” and Cu plating uniformity.

They claim that warpage can be controlled to +/- 0.5mm after carrier debonding. They describe die shift compensation as a “compensable patterning method” which is not described but probably is similar to techniques recently described by Deca [see “Adaptive Patterning for Panelized Processing”]

Little detail is given on how they are going to achieve these requirements.

Nanium – eWLB Dielectric Selection

In eWLB technology  the reliability of the package is a balance of the capability of the different layers that constitutes the package in absorb shocks and mechanical stress from the different materials CTEs. In IC packaging interfaces, the dielectric material, plays a significant role absorbing thermal stress and mechanical shocks slowing down cracks propagation. A wide range of material classes has been considered including PBO, PI, nano-filled Phenol resin, BCB, Silicone, Epoxies, Siloxanes ,  Polynorbornenes and Acrylates. Fifty six56  dielectrics from seventeen manufacturers were compared based on physical, mechanical, thermal, electrical and chemical properties.

They found the most significant material properties are the elongation to break, the tensile strength and the Young’s modulus as they are an indicator of how a polymer will perform under mechanical stress caused by CTE mismatch between the die and the molding compound in thermal cycling and in mechanical shock drop tests.

A PI precursors formulation was selected based on its low curing temperature compatible with eWLB FO-WLP products and processing temperature restrictions. The unidentified PI precursor formulation is NMP/NEP solvent free. It is compatible with copper and all the other chemicals used in production process like solvents, bases and acids. Thus, the PI precursor formulation was selected to be used as buffer layer and also as RDL top layer.

Use of this dielectric reportedly allow  NANIUM to exceed 1,000 cycles in component level based Temperature Cycling Test (TCT -55ºC to 125°C) and 500 to 1,000 cycles, in board-level based Temperature Cycling on Board Test (TCoB -40ºC to 125 °C) according IPC-9701 and JEDEC JESD22-B111 Drop Testing.

Google / Novartis – Wearable electronics for diabetics ?? 

Google and Novartis, announced that  they will create a smart contact lens that contains a low power microchip and an almost invisible, hair-thin electronic circuit. The lens can measure diabetics’ blood sugar levels directly from tear fluid on the surface of the eyeball. The system sends data to a mobile device to keep the individual informed.



The Mountain View CA Google team involved in this program is the stealth  “Google X” group which focuses on “finding new solutions to big global problems” in healthcare and other areas.

For all the latest on 2.5/3DIC and advanced packaging, stay linked to IFTLE…