By Dr. Phil Garrou, Contributing Editor
Samsung Widecon Technology
Samsung introduced us to their Widecon technology in 2014 [link] and it was predicted that this 3D TSV technology linking memory to processor would be introduced in the Exnos 6 generation.
Dick James (Chipworks) recent assessment of the tear own of the Galaxy note 7 [link] tells us that
the application processor that drives this phone is the Exynos 8 Octa (Exynos 8890), similar to the Galaxy S7 and S7 edge. It has an eight-core CPU, with four Samsung designed cores that can run at 2.3 GHz, and four ARM Cortex A53 cores operating at up to 1.6 GHz. Stacked on top of the CPU in the usual package-on-package (PoP) stack, is 4 GB of Samsung LPDDR4 SDRAM. Now that we have 20 nm DRAM processes, the dies are small enough that they are packaged in a 2 x 2 x 2 configuration. The four stacks of two 4-Gb memory dies are mirror-imaged, on both the vertical and horizontal axes.
So – it looks like we are still going to have to wait for the commercial introduction of widecon.
TSMC InFO becomes commercial reality
For several years ow, rumors have been rampant that TSMC scaling of their InFO packaging technology was focused on acessing the highly lucrative Apple iPhone market. For instance see IFTLE 283 “Will Packaging make the Difference for TSMC?”
While a definitive process flow for InFO has not been publically described by TSMC, in IFTLE 261 we reported on a rumored InFO process flow which consists of (1) copper pillar plating on the die, (2) die placed face up on tape, (3)molding to generate reconstituted wafer, (4) polish down to reveal tops of pillars, (5) RDL processing on this polished surface. The capability for finer features than standard fan out packaging reportedly comes from the more planar starting surfaces and better control of the photo processes.
We have also pointed out rumors that ASE would second source an InFO process [see IFTLE 292]
Now a Chipworks teardown confirms the presence of the A10 Fusion chip, manufactured by TSMC with a reported 3.3 billion transistors, in the iPhone 7 link]. Chipworks confirms that the process is a TSMC 16nm finfet based.
“The A10 sits below the Samsung K3RG1G10CM 2-GB LPDDR4 memory. This is similar to the low power mobile DRAM as the one we found in the iPhone 6s. Looking at the X-rays we see the four dies are not stacked, but are spread out across the package. This arrangement keeps the overall package height to a minimum. Assembled in a package-on-package assembly with the A10 InFO packaging technique reduces the total height of PoP significantly”
So the InFO rumors were in fact correct and this in turn will fuel the drive towards HVM of fan out packaging.
ASE Providing SiP for Apple
We had previously noted that ASE was the sole supplier for Apple’s custom-designed SiP modules for used in the Apple Watch. [See IFTLE 238 “ASE & the Apple watch, …”]
Digitimes now reports that ASE, through its Shanghai-based subsidiary Universal Scientific Industrial (USI), has obtained SiP orders for Wi-Fi, fingerprint sensor and force touch modules used in the recently-released iPhone 7 [link].
ASE holds a nearly 80% stake in USI, which has been engaged in backend services for SiP modules.
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