Insights From Leading Edge

Monthly Archives: September 2017

IFTLE 353 Updating CMOS Image Sensor Technology

By Dr. Phil Garrou, Contributing Editor

A few weeks ago, we covered the Sony announcement of the Xperia XZ1, which features a 19MP Exmor RS camera with 960fps video capture and reportedly is fabricated as a stacked 3 layer CIS with DRAM. [see IFTLE 346 “Sony Introduces Stacked Image Sensor with DRAM in Xperia XZ phones]

This technology was first disclosed at IEEE IEM in 2016 as their “Cu2Cu Hybrid Bonding” [link] and discussed in IFTLE coverage of last falls 3D ASIP Conference [see IFTLE 319 “ …3D ASIP Part 2: Image Sensing – Sony, Tessera, SMIC”]

Those of us that have been following 3DIC for the past decade recognize this as the Ziptronix “DBI process” which they licensed to Sony a few years ago. It is now quite clear that the literature is generically calling this technology “hybrid bonding” since the bonding occurs to a surface containing both copper and oxide. Hybrid bonding does not have TSVs since it simultaneously connects the two substrates physically and electrically.

They depict there process flow as follows

Sony 1

The trench and via are made at the BEOL top layer of each wafer. Then, barrier metal and Cu seed are formed by PVD. Cu is plated up and annealed at the appropriate temperature. Excess Cu is removed by CMP to reveal the Cu connection pads and oxide dielectric. After face-to-face bonding, the wafer stack is annealed. As illustrated in their figure 4, the upper Cu pad and lower Cu pad are connected by Cu diffusion and grain growth, and the upper dielectric and lower dielectric are connected by dehydration-condensation reaction. They report that it is important to remove any voids from the Cu pad bonding interface during the post-ECD annealing.

Samsung CIS now include Stacked DRAM too

According to new reports [link], Samsung has developed and will begin mass production in November 2017 of a similar mobile camera sensor capable of 1,000 frames per second (FPS). Reports are that the camera contains a stacked 3 layer image sensor, with the layers made up of the sensor itself, logic chip, plus a DRAM chip that can temporarily store data.

While we are at it, let’s take a look at the advances covered at the recent Int Image Sensor Wkshp held in Hiroshima this past May.


Venezia of Omnivision described their “1.0um pixel improvements with hybrid bond stacking technology” discussing their Gen2, 1.0um CMOS image-sensor technology featuring hybrid bonding stacking.

Their first generation, stacked chip technology used oxide-oxide bonding and TSV to bond and electrically connect the sensor and logic wafers, respectively. “With stacking technology, the logic circuitry is placed under the array, resulting in an overall smaller chip size than is possible with standard BSI-CIS; where the circuit is located on the same wafer. Stacking also allows for sensor-only processes that improve CIS performance which could have negative impacts on circuit performance in a BSI-only process.”

The gen 2 technology uses hybrid bonding “where wafers-to-wafer bonding occurs at both the oxide and metal interfaces, and water-to-wafer interconnection is made at the top metal bonding pad. This architecture offers a better interconnect pitch and more flexible interconnect placement than the previous Gen1 approach. For instance, bonding can occur closer to the array edge, or even within the array.” The resulting chip size is 10% smaller using HB technology for the Gen2 1.0um, 16MP product.

fig 2



Hseih of TSMC gave a joint paper with Qualcomm on “A 3D Stacked Programmable Image Processing Engine in a 40nm Logic Process with a Detector Array in a 45nm CMOS Image Sensor Technologies”

They designed & fabricated a RICA (Reconfigurable Instruction Cell Array) ASIC wafer stacked with a pixel arrays wafer of 8MP, 1.1 um pitch BSI image sensor test vehicle. This device used “the 3D stacking technologies of a 45nm CIS process and a 40nm logic process at TSMC”.


Kagawa of Sony discussed “Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding” further detailing their Cu2Cu hybrid bonding technology.

They describe the positive attribute of not having to create TSVs in their devices as follows “Making TSVs needs special fabrication equipment, such as deep Si etcher and high coverage metal/dielectric deposition tool. In addition to the fabrication problems, there are device problems. In particular,

the keep-out-zone (KOZ) strongly affects device specifications and circuit design. On the other hand, hybrid bonding does not have such problems. It can basically be fabricated by the conventional back-end-of-line (BEOL) process, and special equipment is never needed….Moreover, the Cu connection pad is located on top of the BEOL layer, and it never interferes with the MOS-FET during the fabrication process. It enables enormous circuit design flexibility and further chip size reduction can easily be achieved.”

Reliability tests were carried out under voltage and temperature stressed conditions. Predicted lifetime was estimated from Black’s equation as over 10 years. Extremely low leakage current and good TDDB reportedly indicate that the Cu connections are well isolated by the dielectric. They fabricated a stacked back-illuminated CMOS image sensor with “22.5 megapixel 1/2.6 size CIS featuring a 1.0μm unit pixel size and an ISP…” using their Cu2Cu hybrid bonding process.


Ray Fontaine of TechInsights in his “Survey of Enabling Technologies in Successful Consumer Digital Imaging Products” detailed the technologies responsible for the remarkable advances in mobile phone camera performance over the last decade.

He notes that “Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips” and adds that “The recent manufacturing trend for back-illuminated CIS chips in a stacked configuration seems to have stabilized at the 90/65 nm process generation “ as shown in the fig below.

Techinsights 1

He notes that Sony’s current leadership position in the industry is due to the fact that they were the first to bring stacked CIS chips to market, by implementing homogenous wafer-to-wafer bonding (oxide bonding) with TSVs in 2013 and Cu-to-Cu hybrid bonding, (also known as Cu2Cu bonding or DBI), in 2016. OmniVision’s first observed stacked chips, fabricated with foundry partner XMC in 2015, used a ‘butted’ TSV structure in which a single, wide TSV contacted both a CIS and ISP pad structure. OmniVision later adopted a unified TSV structure for its 1.0 μm pixel generation PureCelPlus-S chips, fabricated by foundry partner TSMC. The observed Samsung stacked chips in production also feature a butted TSV structure, but instead use a W-based TSV window liner for vertical interconnect. These are shown below.

techinsights 2

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 351 ASE Tech Forum Part 3: Plasma Dicing, 2.5/3D Options

By Dr. Phil Garrou, Contributing Editor

Several of you have asked how Hannah, Madeline and family have survived the floods down in Houston. Thanks for your concern. Luckily, the old time Texans built Rice University on high ground and my son bought in a neighborhood near there. However, that doesn’t mean they didn’t see water. The pic below shows Maddie standing on the sidewalk outside their house knee deep in water, but, as you can see to the right, it was nothing compared to other parts of the city!




Finishing off our look at the ASE Tech Forum, Plasma-therm (working with ON Semi and DISCO) examined Plasma die singulation. One would look to plasma dicing to avoid the damage caused by mechanical blade dicing or the HAZ caused by Laser dicing which requires as larger than normal street to act as a keep out zone. Stress is also reduced by plasma dicing as is shown in the figure below. It is also clear that plasma dicing can result in more die per wafer due to the smaller required street/kerf.

plasmatherm 1


However, plasma dicing cannot etch through metal so any features in the streets (such as test structures) must be dealt with.

One solution is to isolate the test structures and process control monitors and etch around the die as shown in the fig below.

plasma-therm 2

In terms of market adoption of plasma dicing, they offered the following slide showing us what was qualified in production and what was in development.

plasmatherm 2

2.5 / 3D Technology Choices

ASE’s Chris Zinck in his examination of 3D packaging presented an interesting slide on 2.5/3D options plotting technology solutions vs substrate L/S capability. It is shown below. In their view what is evolving is a technology choice based on required density with std FC and PoP at > 10um; fan out using advanced laminate silicon-less RDL solutions between 10um and 1um and silicon interposers at less that 1 um. IFTLE is not so sure about the advanced substrate solutions in the 3-1um range , but in general this is a good way of looking at how the market is breaking out.


IMAPS 50th in Raleigh

Hope to see many of you at this years fall IMAPS meeting which just so happens to be the 50th anniversary of IMAPS and just so happens to be down the road from me in Raleigh NC. As I explained a few blogs ago [see IFTLE 336 “ISHM to IMAPS…” ] IMAPS has been there since the beginning of our industry and it will be fun to see all of those who have contributed to packaging through the years.



For all the latest in advanced packaging, see you at IMAPS 2017 and, of course, keep reading IFTLE…

IFTLE 350 DARPA Electronics Resurgence Initiative: Going Beyond Moore’s Law

By Dr. Phil Garrou, Contributing Editor

IFTLE has discussed in detail the coming end of Moore’s Law and the implications that holds for our electronics industry. For instance see IFTLE 300 “ITRS 2.0 – It’s the End of the World As We Know It”,

Well DoDs DARPA has stepped up and is attempting to lead the industry out of the quagmire that is the myriad of options that have presented themselves.

On June 1, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling”. Key to the ERI will hopefully be new collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

For details on the ERI see DARPA-SN-17-60 [link]

chappellThe program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced “For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests. ”He continued “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support”.

The design portion of the initiative will focus on developing tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these application-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.


As part of this overall Electronics Resurgence Initiative, DARPA, last week, had their kick of meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). We have previously discussed CHIPS here [see IFTLE 323 “The New DARPA Program “CHIPS”…”

The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State University.

The CHIPS program will tackle digital interfaces and systems and their supporting technologies with the goal of:

– developing common interface standards                                                                                                                                                    – enabling the assembly of systems from modular IP blocks                                                                                                               – demonstrating the reusability of the modular IP blocks via rapid design iteration


For all the latest in advanced packaging, stay linked to IFTLE…