EUVL Focus

Monthly Archives: September 2012

Moving forward with Moore’s Law: Analysis of EUVL investments by chipmakers

There have been recent announcements by leading chip-makers of very large investments in ASML.  The company has received investments of  3 billion euro in equity and 1.3 billion euro for R&D for its next-generation EUVL and 450 mm tools. The first announcement was made by Intel in July, followed by similar statements from TSMC and Samsung.

These investments are obviously a very good thing for ASML. They demonstrate chipmakers’ confidence in the company and willingness to support ASML in producing leading-edge scanners. ASML took a risk by investing heavily in EUVL, but it seems to be paying off in terms of financial support and increasing orders for EUVL scanners. But there is more to this story, which I will explain below.
1. While Intel invested 3.3 billion euro in ASML, it simultaneously made a much smaller investment in Nikon to develop 450 mm scanners! This further indicates ASML’s growing importance as the ONLY supplier of leading-edge EUVL scanners, along with its being the world’s # 1 scanner maker. This is a significant change in the industry model, which has been used to having two suppliers for critical scanning tools. Having only one supplier for the most critical chipmaking equipment poses some risks for manufacturers, and that may be the reason for ASML’s equity co-investment program – although the company says that “voting rights of customer shareholders are restricted.”  Also, ASML says the “results of these development programs will be available to every semiconductor manufacturer with no restrictions,” hence it’s a good thing for the entire industry.
2. Intel, TSMC and Samsung will be the first recipients of EUVL scanners and will be ahead of others in making advanced semiconductors –  ensuring their positions as leading-edge chip-makers. Other chip-makers planning to use EUVL – Toshiba, GlobalFoundries, IBM and Hynix – most probably will be next in line for scanners.
3. 450mm is looking like a sure thing, and the recent investments show that it’s likely next-generation EUVL scanners will support 450mm. The transition to 450mm is going to be very expensive, but Moore’s Law must move forward and we have to depend on the known enablers of increasing wafer size and decreasing source wavelength. I mentioned in the press in 1999 that “transition to 300 mm is not optional.” In the same article, I estimated the next wafer size as 450 mm. Almost a dozen years later, the 450 mm transition is running full speed! No one said the route to Moore’s Law is going to be easy, but this may be the only road we have and the industry will need to adjust to new economic models.  
4. Although chipmakers have invested heavily in ASML, the supplier integrates but does not make EUV sources. So 1.3 billion euro will go toward developing parts for ASML’s tools. Hence, it is not clear how this investment is going to help with the issue of source power.
Do EUVL investments adequately address the technical challenges?
EUVL early insertion by 2014 is not without risk. Some things about the industry’s investment strategy will need to change if we want EUVL in high-volume manufacturing (HVM) sooner rather than later. To insert EUVL into HVM, we need not only technical viability (proven for a few years) but also cost benefit (not yet fully proven).  EUVL can print better than competing technologies but must print with sufficient yield to a better or comparable cost to competing technology – double or quadruple 193 nm immersion.
In order to discuss this further, let’s do a quick review of the current leading challenges of EUVL:
#1 Source (average power, dose stability and uptime)
#2 Mask (defect density, inspection tools and sources for inspection tools)
#3 Resist (line edge roughness [LER], sensitivity and resolution)
Optics is a fourth issue, but its challenges are considered well addressed by Carl Zeiss. Assembly of EUVL scanners themselves are well in hand at ASML.  Other challenges also will be overcome, but we need an order of magnitude improvement to deliver 100 W sources.
It should be noted that in addition to its recent investments, the industry also has committed $150 million in the last two years for mask inspection tools, and this year announced more support for developing high numerical aperture (NA) EUV optics.
However, the investment in the #1 issue of EUV sources has been a BIG ZERO. The industry’s assumption has been that source suppliers will address this challenge and no other action is needed. With billions of dollars going into solving lesser issues, this investment approach is bit flawed. No wonder EUVL scanners are delayed – how can they be otherwise? EUV source suppliers are working very hard and investing heavily on their own, but this is a difficult challenge and suppliers will benefit from new solutions that they can engineer into products.  Sources have not met the needed 100 W target, and I think it will take few more years to get there. I doubt that higher power targets will be met with current technical approaches, and without fresh investment in new technologies.
Chipmakers can continue to ignore this topic, but they have already paid a price in terms of the delay in HVM insertion, and will continue paying with further delays in EUV readiness and lower throughput as they enter into HVM. I think there are insertion paths for EUVL scanners with < 100 W sources, but the ROI will not be very good. Can’t we do better?
Some will say that chipmakers are doing all they can. EUV sources are plasma-based, and chip manufacturers are not experts in plasma physics and don’t fully know what to do with it. However, they have funded EUVL R&D in other areas through various consortia with very significant budgets. Yet no one has any R&D programs to generate new solutions for source technology. In short, chip-akers have a flawed investment strategy which is going to continue costing them. I believe that the industry model on this issue must change. Chipmakers need to be proactive in ensuring that sources not only deliver power today, but also that there are enough new ideas in the pipeline so that tomorrow’s 250 to 1000 W sources will be available when we need them. They are already spending hundreds of millions in R&D; why not invest in generating new approaches to our #1 issue?
EUVL investment is growing, but the source challenge remains. Although EUVL’s place is set as the leading technology for next-generation lithography (NGL), we need to know what will happen to EUVL insertion timing if sources continue to develop at their current rate. How can we bring EUVL into HVM sooner? These are topics on which I will share my opinions in future blogs at this website.