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Monthly Archives: October 2012

IFTLE 120: SEMICON Taiwan 2012, part 1

This year’s 3DIC forum at SEMICON Taiwan was entitled “3D-IC Supply Chain Readiness.” With most industry leaders who are currently involved in 3D development believing that the realization of 3D-IC technology into high-volume manufacturing is not a question of “if” but rather only a question of “when,” this year’s forum was focused on industrial readiness and infrastructure maturity. Representatives from manufacturing supply chains, ranging from EDA to foundry/OSAT, shared their views through presentations and an open panel.

Dr. Ho Ming Tong (left) , general manager and chief R&D officer of ASE and Dr Mike Ma, VP of Corporate R&D for Siliconware, chaired the Symposium and delivered opening remarks. Speakers included Amkor, Aptina, Cadence, EVG, LSI, Teradyne, Tohoku-MicroTec, UMC, and Xilinx


Kurt Huang gave a presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking” — making it clear that they will be ready to compete with TSMC in the foundry interposer and 3D stacking business.

Recall UMC has been looking at the 3DIC area for quite a while, having been in a developmental relationship with Elpida and PTI [see IFTLE 8, “3DInfrastructure, Announcements and Rumors”] since 2010.

UMC envisions several work flow models (shown below) and concludes that each OSAT / foundry will have their own capabilities and preferences.

UMC indicates that their foundry design rules for interposer fabrication are ready to go, with product level packaging & testing and reliability assessment scheduled for completion in 4Q 2012.

Typical 3D TSVs are 6 �? 50 and for interposer are 10 �? 100 um. KOZ have been determined to be 5μm for 28nm HKMG core device with TSV pitch: JESD229 50/40μm.


Min Yoo of Amkor Taiwan gave a presentation entitled “3D IC Technology: The OSAT Perspective.” Amkor sees: (1) partitioning logic blocks into higher-yielding sub-blocks as is being done by Xilinx and others in the FPGA arena — this results in lower cost 28nm products as well as chips that are less sensitive to 28nm processing issues; and (2) repartitioning SoC devices into separate functions which allows for using the latest node (i.e. 28nm) only where it is required. The latter has been discussed previously by Bryan Black of AMD [see IFTLE 80, “GIT@GIT”].

Also of interest is the Amkor roadmap showing Application processors + DDR for smartphones and tablets being scheduled for 2014.

Amkor, as expected, is in favor of a supply chain where the TSV are fabricated by the fab / foundry and then shipped to the OSAT for subsequent processing.

They highlight the fact that they are involved with the current Xilinx FPGA product . Their copper pillar μbump technology is commercial at 40μm, demonstrated at 30μm, and in development at 20μm.

We will continue with more presentations from SEMICON Taiwan next week.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE……………………………………

IFTLE 119 ICECool Puts 3D Thermal Issues back in Focus

Keeping it Cool

Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins’ article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50μm is required to deal with the local hot spots on the thermal test chip they used.

Their study on the impact of TSVs on the temperature profile in the test chips showed that the presence of the die-die connections, such as Cu or CuSn microbumps or direct Cu-Cu bonds, is more important than the presence of the TSVs itself. The Cu TSVs with high thermal conductivity (390 W/mK) are inserted in the Si, which is conductive (150 W/mK at room temperature and120 W/mK at the operating temperature). Conductivity values for the underfill materials are typically 0.2 W/mK for unfilled underfills and 0.3-0.4 W/mK for filled underfills, depending on the amount and type of filler particles. The difference in thermal conductivity between the metallic bonds and the adhesive material is thus two orders of magnitude. As a result, "well placed dummy microbumps, rather than dummy TSVs, can be used to increase the effective thermal conductivity and to reduce the temperature increase in a 3D stack."

Many of you are aware of DARPA’s BAA 12-50 ICECool an effort of CALCE’s Avi Bar-Cohen within DARPA’s Microsystems Technology Office (MTO). ICECool Fundamentals is the initial thrust and first BAA of DARPA’s ICECool program.

The specific goal of ICECool Fundamentals is to demonstrate chip-level heat removal in excess of 1 kW/cm2 heat flux and 1 kW/cm3 heat density with thermal control of local sub mm hot spots with heat flux exceeding 5 kW/cm2, while maintaining these components in their usually accepted temperature range by judicious combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects. ICECool Fundamentals is, thus, the first step toward achieving the system performance goals of the ICECool program and will develop the fundamental building blocks of intrachip and interchip evaporative microfluidic cooling.

ICECool Fundamentals will, over an anticipated 24–36 months, develop and demonstrate the microfabrication techniques needed to implement thermal interconnects and evaporative microfluidics in multiply-microchanneled semiconductor chips, and study, model, and correlate intrachip heat diffusion and the thermofluidic characteristics of evaporative flows in microchannel flow loops within individual chips and/or in the microgaps between chips in 3D stacks — without compromising the combination of intra- and/or interchip microfluidic cooling and on-chip thermal interconnects in one of several possible semiconductor wafers.

They offer the following schematic as an interchip approach:

and required responses to deliver on the following metrics.

There will be several winners to this first "fundamentals" BAA and hopefully we will be seeing the next generation 3DIC thermal stacking technology evolve from the government-supported program. IFTLE will keep you informed as the winners are announced and their proposed thermal solutions become public.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………………………..

IFTLE 118 IMAPS 2012 part 2

Continuing our look at 3D and advanced packaging presentations at IMAPS 2012.

Shinko and CEA Leti

With the recent announcements by Xilinx, Altera and others the commercial production of 2.5D products on "high density" interposers is entering the realm of commercial reality. While it is clear that fine featured interpsoers will come from foundries like TSMC, there have been questions, about "coarse featured" interposers in terms of who will make them and what applications they will be used in. [see IFTLE 94, "Experts discuss interposer Infrastructure at IMAPS Device Pkging Conf"]

Shinko and Leti now describe integration and electrical characterization of such a "coarse featured" 3D silicon Interposer demonstrator for a SiP application. This demonstrator consists of (4) 10 Ã?? 10 mm chips mounted on a 26 Ã?? 26 mm Si interposer with 25µm microbumps on 50µm pitch and underfilled. TSV diameter are 10µm and interposer thickness is 100µm for an Aspect Ratio (AR) of 10. We are told that RDL on both sides of the interposer are done with a "semi additive process" although we are not given line width or pitch. We assume these are "coarse pitch" meaning 5µm or greater.

The populated interposer is then mounted on the PWB using Sn-57Bi solder to achieve low temp reflow. These packaged test structures were tested for TSV continuity and via chain resistance. These packages also survived 100 hrs at 125°C, 1000 cycles from -55 to 125°C, and 1000 hrs of HAST.

IBM Japan

IBM Japan reported on the warpage and mechanical stresses generated during chip and interposer assembly processes. Chip and package assumptions are shown below.

They modeled the following sequences:

Sequences are each divided into two steps, with either chip joining or interposer joining being the first step.

In the chips first sequence, interposer warpage is caused by CTE mismatch between interposer and RDL. Results are highly dependent on the thickness of the interposer. A 100µm to 200µm thick interposer can have more than 200µm displacement which will make it difficult to mount to the organic substrate. Underfill between the chips and interposer inhibits warpage.

Warpage of the interposer in the interposer to laminate first sequence is convex. A 100µm glass interposer shows less displacement than silicon.

The evaluated Von Mises stress on the interposer to substrate solder balls and found the largest stress was developed by the thickest silicon interposer and the lowest on the thinnest glass interposer.


In their paper "Stacking Aspects in the View of Scaling", IMEC points out that when pitch goes below 40µm "stacking accuracy is one of the main drivers to ensure yielding devices." It is shown that stacking can be made less sensitive to in plane misalignment by the obvious options of increasing the pad size or decreasing the solder bump size, i.e. making the landing pads on the interposer larger than the bumps on the chip makes up for misalignment.

In a second presentation, "Small pitch microbumping and experimental investigation for underfilling 3D stacks," they report on 3D stacking characterization when using pre applied underfill.

For 3D stacking capillary underfilling has clear limits in terms of the gap between die and the bump pitch. This limits high density integration and therefore shifts focus onto pre applied underfill where the material is dispensed on the landing die before stacking. Pre-applied UF does have concerns such as transparency for alignment marks and UF/filler entrapment between bumps.

IMECs studies reveal that both NUF/NCP (define) and WUF (wafer underfill) have commercial products that result in >90% electrical yield after underfilling, although issues such as delamination of WUF films was observed.

Thin chip stacking using B2F technology

For many years PFTLE and IFTLE have been proponents of die thinning for 3D IC stacks because it not only has an effect on the final thickness of the product, but also has a direct effect on the TSV AR. When die are thinned to i.e. 25µm they can be stacked B2F without TSV and metallized over the edge to make interconnect. This technology was first described by Toepper from Fraunhoffer IZM.

In this presentation, ST Micro, CEA Leti, Datacon, Disco, and EVG presented two approaches have been investigated for B2F bonding of the thinned die: (1) applying a die attach film (DAF) bonding layer, or (2) using spin coated polymers for the die attach.

Thin die prep is required. In order to obtain good step coverage, die are singulated at 45° to provide edge slope. Once mounted on tape, plasma stress relief is applied. Without plasma treatment of the backside and edges, they found 100% of the die broke during the subsequent pick and place operation.

Using DAF is an acceptable solution but placement accuracy was degraded due to the presence of the DAF under the die and tool clogging by the DAF.

Spin-on polymer was found to be a better solution. They examined BCB, PI, and AL-X . PI showed outgassing and AL-X was not tacky enough so they down selected BCB.

For a capping insulation layer they examined: (1) conformal encapsulation by CVD low temp oxide; (2) thin conformal encapsulation by spin or spray coated polymeric films; and (3) thicker planarizing encapsulation using spin on polymers. The best solutions were found to be: (a) 200-240 C LTO in combination with the BCB adhesive layer, or (b) spray coating of positive, photo WPR 5100 from JSR. JSR thick resist THB151N was used to make contact from the top to the bottom chip.

For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………..

IFTLE 117: Tezzaron acquires SVTC fab; 3DIC activity at IMAPS 2012 part 1

Tezzaron acquires Texas SVTC facility

Bob Patti of Tezzaron Semiconductor has been touting the merits of 3DIC for longer than most everyone else in our industry. Bob first announced a partnership with Chartered Semi to scale up his memory through-silicon via (TSV) technology back in 2007 [see PFTLE13: "50$ bonding and Intel announces ‘We are ready‘"].

Tezzaron has always been at the leading edge, offering 2µm pitch W TSV several years ago. Being ahead of the industry, frankly, they have had issues working through the regular supply chain.

Last week Tezzaron took a major step toward alleviating that problem with the announcement that it is acquiring the wafer fabrication facility of SVTC Technologies in Austin, Texas. You old-timers will recall this as the SEMATECH fab in Austin. Tezzaron will continue the operation of this facility while adding capabilities to assemble its own 3DIC devices. Tezzaron indicates that they will be operating the fab with the same employees in the same location.

IMAPS 2012

The 45th Symposium on Microelectronics (IMAPS 2012) was held a few weeks ago in San Diego. Let’s look at some of the 3D and advanced packaging papers presented at this meeting.


When last we discussed Qualcomm it was complaining about constrained supply of 28nm [ see IFTLE 114, "…28nm; nickels and a symbiotic relationship"] but do we have any clarity on exactly what it is trying to build? Maybe now we do.

Gu and co-workers at Qualcomm reported on a memory on logic 3DIC stack consisting of a two-chip-wide IO memory stack bonded to a 28nm logic chip.

TSV are 6µm, wafers are thinned to 50µm, TSV connection is to M1 of the 7-layer copper/low-k interconnect stack. The memory stack has 1200 IO on 40µm pitch. The bottom memory die has TSV, the top die does not need them. Thinned die are shipped either on their carrier (OSAT removes the carrier) or after removal from the carrier on a flex frame.

Negligible shift in electrical parameters are observed after optimizing TSV formation and determining the need for a 5µm keep-out zone (KOZ). No change in bump resistance is seen after 1000 hrs at 150°C and 1000 cycles of temp cycling. Memory function was verified after full assembly of the stack.


Xilinx has been releasing information on its 2.5D FPGA module for the past two years. [See IFTLE 73, "Xilinx shows 2.5D Virtex 7 at IMAPS 2011" and IFTLE 23, "Xilinx 28nm multi-die FPGA, copper pillar advances at Amkor, and Intel looking at foundry options."]

In this latest presentation, Banijamail and co-workers examine the reliability of their 2.5D Virtex-7 H580T which consists of a transceiver chip and two FPGA slices. Interposer TSV are 10-20µm and 50-100µm deep. FPGA chips are bumped on 30-60µm pitch using Cu pillar bump technology.

Different substrate sizes and designs, lid designs, lid materials, and underfills were examined to minimize warpage and maximize microbump and c4 bump reliability. Control of these variables resulted in packages that met JEDEC warpage spec and minimized BGA fatigue.

Applied Materials

IFTLE has detailed many times how Applied Materials is making 3DIC a focus area for its equipment business. [see IFTLE 95, "Time flies when you’re having fun: Further details on the Micron HMC, equipment suppliers continue consolidation, EVG temp adhesive open platform" and PFTLE 72, "Samsung 3-D ‘roadmap’ that isn’t."]

Eaton and co-workers from Applied Materials now present process detail on how scallop-free TSV can be etched in their Silva etch chamber. Complete scallop removal added ~10-15% to the time to etch a 10 Ã?? 100 TSV with 30nm sidewall scallops.


SEMATECH reported on their examination of the copper protrusion issue. While they quote a few past references such as my friends Paul Ho and Jay Im at UT Austin, to give credit where credit is due, they leave out what I think are the key references to the area [see "Researchers strive for copper TSV reliability," Semiconductor International, Dec. 3rd 2009], which include Bob Patti at Tezzaron whose cross-sections first brought the protrusion question to the public eye; Paul SibelrudPaul Sibelrud (then at Semitool) who extensively studied the extent of the problem and the composition of the extrusions; and most importantly Eric Beyne at IMEC who was the first to disclose the thermal anneal solution for the problem.

For those of you new to the area, after TSV are filled with copper and planarized by CMP they are subsequently exposed to >350°C downstream processing during which time Cu, due to a higher CTE, expands more that the surrounding silicon and extrudes out beyond the planarization point and stays there upon cooling due to its plastic deformation properties. This expansion also causes stresses to be generated which in turn require a KOZ (keep-out zone) to be defined so said stresses do not negatively impact the transistor electrical performance.

The goal of this SEMATECH study was to look for "possible mechanisms that cause copper protrusions by varying process conditions." The TSVs studied were 5 Ã?? 50 lined with 500nm of TEOS oxide and Ta/TaN diffusion barrier, which were then annealed at 150°C for an hour and CMP’ed. Samples post CMP were annealed at seven different temperatures .

The researchers outline a number of methods of detecting the protrusions and give +/- for them. They chose optical imaging and AFM as their methods of choice and micro raman spectroscopy to determine post-CMP anneal stress.

As expected, stress increases as the post anneal temp increases and copper protrusions range from 50nm to 400nm when annealed (post plating) from 150°C to 400°C. In agreement with the previous studies by Sibelrud, they find that plating bath chemistry has a major impact on protrusion. They link this to whether the copper is in a tensile or compressive state. They suggest that copper grown in a tensile stress state is a significant contribution to protrusions after thermal annealing at high temperature.

Next week we will finish our look at IMAPS 2012.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………………….