Continuing our look at 3D and advanced packaging presentations at IMAPS 2012
Shinko and CEA Leti
With the recent announcements by Xilinx, Altera and others the commercial production of 2.5D products on "high density" interposers is entering the realm of commercial reality. While it is clear that fine featured interpsoers will come from foundries like TSMC, there have been questions, about "coarse featured" interposers in terms of who will make them and what applications they will be used in. [see IFTLE 94, "Experts discuss interposer Infrastructure at IMAPS Device Pkging Conf"]
Shinko and Leti now describe integration and electrical characterization of such a "coarse featured" 3D silicon Interposer demonstrator for a SiP application. This demonstrator consists of (4) 10 Ã?? 10 mm chips mounted on a 26 Ã?? 26 mm Si interposer with 25µm microbumps on 50µm pitch and underfilled. TSV diameter are 10µm and interposer thickness is 100µm for an Aspect Ratio (AR) of 10. We are told that RDL on both sides of the interposer are done with a "semi additive process" although we are not given line width or pitch. We assume these are "coarse pitch" meaning 5µm or greater.
The populated interposer is then mounted on the PWB using Sn-57Bi solder to achieve low temp reflow. These packaged test structures were tested for TSV continuity and via chain resistance. These packages also survived 100 hrs at 125°C, 1000 cycles from -55 to 125°C, and 1000 hrs of HAST.
IBM Japan reported on the warpage and mechanical stresses generated during chip and interposer assembly processes. Chip and package assumptions are shown below.
They modeled the following sequences:
Sequences are each divided into two steps, with either chip joining or interposer joining being the first step.
In the chips first sequence, interposer warpage is caused by CTE mismatch between interposer and RDL. Results are highly dependent on the thickness of the interposer. A 100µm to 200µm thick interposer can have more than 200µm displacement which will make it difficult to mount to the organic substrate. Underfill between the chips and interposer inhibits warpage.
Warpage of the interposer in the interposer to laminate first sequence is convex. A 100µm glass interposer shows less displacement than silicon.
The evaluated Von Mises stress on the interposer to substrate solder balls and found the largest stress was developed by the thickest silicon interposer and the lowest on the thinnest glass interposer.
In their paper "Stacking Aspects in the View of Scaling", IMEC points out that when pitch goes below 40µm "stacking accuracy is one of the main drivers to ensure yielding devices." It is shown that stacking can be made less sensitive to in plane misalignment by the obvious options of increasing the pad size or decreasing the solder bump size, i.e. making the landing pads on the interposer larger than the bumps on the chip makes up for misalignment.
In a second presentation, "Small pitch microbumping and experimental investigation for underfilling 3D stacks," they report on 3D stacking characterization when using pre applied underfill.
For 3D stacking capillary underfilling has clear limits in terms of the gap between die and the bump pitch. This limits high density integration and therefore shifts focus onto pre applied underfill where the material is dispensed on the landing die before stacking. Pre-applied UF does have concerns such as transparency for alignment marks and UF/filler entrapment between bumps.
IMECs studies reveal that both NUF/NCP (define) and WUF (wafer underfill) have commercial products that result in >90% electrical yield after underfilling, although issues such as delamination of WUF films was observed.
Thin chip stacking using B2F technology
For many years PFTLE and IFTLE have been proponents of die thinning for 3D IC stacks because it not only has an effect on the final thickness of the product, but also has a direct effect on the TSV AR. When die are thinned to i.e. 25µm they can be stacked B2F without TSV and metallized over the edge to make interconnect. This technology was first described by Toepper from Fraunhoffer IZM.
In this presentation, ST Micro, CEA Leti, Datacon, Disco, and EVG presented two approaches have been investigated for B2F bonding of the thinned die: (1) applying a die attach film (DAF) bonding layer, or (2) using spin coated polymers for the die attach.
Thin die prep is required. In order to obtain good step coverage, die are singulated at 45° to provide edge slope. Once mounted on tape, plasma stress relief is applied. Without plasma treatment of the backside and edges, they found 100% of the die broke during the subsequent pick and place operation.
Using DAF is an acceptable solution but placement accuracy was degraded due to the presence of the DAF under the die and tool clogging by the DAF.
Spin-on polymer was found to be a better solution. They examined BCB, PI, and AL-X . PI showed outgassing and AL-X was not tacky enough so they down selected BCB.
For a capping insulation layer they examined: (1) conformal encapsulation by CVD low temp oxide; (2) thin conformal encapsulation by spin or spray coated polymeric films; and (3) thicker planarizing encapsulation using spin on polymers. The best solutions were found to be: (a) 200-240 C LTO in combination with the BCB adhesive layer, or (b) spray coating of positive, photo WPR 5100 from JSR. JSR thick resist THB151N was used to make contact from the top to the bottom chip.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE………………..