Insights From Leading Edge

Monthly Archives: October 2013

IFTLE 167 IARPA Trusted Integrated Chips program (TIC); The Apple A7


In the US, we are approaching Oct 31, the day for pumpkins and witches. Hannah and Madeline wish all IFTLE readers a Happy Halloween.

H and M

IARPA Trusted Integrated Chips

At the IEEE 3DIC in San Francisco Dan Radack of IDA [Institute of Defense Analysis] recently gave an update on the  IARPA trusted Integrated Chip Program known as TIC


From 19996 – 2006 the IC Fab at Ft Meade was used to fabricate ICs required for Govt. programs. It was mothballed 5-6 years ago. From 2003 to present the Govt. has used so called “trusted foundries” but they found that they were not able to provide everything that the Govt. needed.

With all of the top foundries now situated outside the US or owned by non US entities, there was a need for a new way of ensuring secure state of the art chip procurement. This certainly dovetailed with the interest in cyber security i.e. how to prevent counterfeits and the vision of needing more-than-Moore technology (i.e. sensors in a 3D chip stack) in the future.

Trusted Integrated Chips program TIC

In the summer of 2011 The Intelligence Advanced Research Projects Activity (IARPA) announced its  Trusted Integrated Chips program. TIC features what IARPA calls “split-manufacturing,” where fabrication of new chips is divided into Front-End-of-Line (FEOL) manufacturing consisting of transistor layers to be fabricated by offshore state-of-the-art” foundries lines and Back-End-of-Line (BEOL) development that would be fabricated by trusted U.S. facilities.

In this approach, the design intention is not disclosed to the FEOL fabricators. “FEOL circuit fabrication to the point of only the first metallization layer can be used to obfuscate the design and performance of an integrated chip thereby protecting the intellectual property of the designer. Alternately, circuit obfuscation can be realized through a chip integration strategy whereby only partial circuits are fabricated on any single chip but when integrated with other chips or wafers in a US manufacturing or packaging facility, a complete safe and secure circuit or system can be realized,” IARPA stated.

According to IARPA, the vision of the TIC Program is to ensure that the United States can:

• obtain the highest performance possible in integrated circuits;

• obtain near 100% assurance that designs are safe and secure — not compromised with malicious circuitry;

• ensure security of designs, capability, and performance while simultaneously protecting intellectual property; and

• realize secure systems combining advanced CMOS with other high value chips.

The TIC program is examining  a number of split-manufacturing concepts in the following areas:

• Mixed Signal                       • Photonics-CMOS                       • MEMS-CMOS

• Power-CMOS                      • RF CMOS                                  • Memory-CMOS

• Josephson Junctions-CMOS                    • Other systems integrated with CMOS

The five-year program was divided into three phases with the development and demonstration of split-manufacturing starting at the 130 nm technology node in Phase 1. It is anticipated that the TIC Program performers will scale the development of their capabilities to the 22 nm node at the end of a five-year period in Phase 3.

Sandia National Laboratories was selected to coordinate the FEOL and BEOL processing with Multi-Project Wafer runs carried out by the University of Southern California/Information Sciences Institute (USC/ISI) using their MOSIS service.

6 organizations did design of CMOS circuits in the MPW multi project wafer. Global foundries performed the front end work and  IBM Burlington fabricated the interconnect layers. Each of the 6 designers then capped the structure with their heterogeneous layer.

NGAS, Cornell, Lucent, Raytheon Vision systems, CMU, Stanford

Raytheon capped with focal plane array for vision system

Carnegie Mellon – cap with piezoelectric MEMS containing digital, analog and smart SRAM

Bell Labs / Lucent – cap in photonics layer

Northrup Grumman – InP mm wave circuits

Cornell – FPGA with ultrasonic comm. Cap

Stanford – cap with materials and ReRam (resistive RAM)

The program is now moving to 65 nm. The move to 28nm will be June or 2014

Details on the Apple A7

The Apple A7 is a PoP 64-bit SoC designed by Apple.  It first appeared in the iPhone 5S, which was introduced in September 2013. Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor, the Apple A6. The A7 is a 64-bit 1.3GHz dual-core CPU coupled with what’s believed to be a Power VR G6430 GPU. The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size.


Fellow blogger Dick  James from Chipworks has sent the first shots of the PoP processor. He comments that  “”It looks as though there is some degree of bowing in the top package, and there is an interface layer between the two packages. Another surprise is silver wire in the Elpida DRAM package..the pitch of the TMV (through mold via) between the top and bottom packages is 0.35mm. Ball pitch on the base is 0.4mm. There are 3 rows of TMVs for a total of 456. Ball count on the base is 34 x 38 = 1292.”

Cross section of the A7 is shown below.


For all the latest on 3DIC and advanced packaging, stay linked to IFTLE.

IFTLE 166 IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati

The IEEE 3D System Integration Conference  met recently in SF to hold their 4th annual symposium. The conference which is held on a rotational basis in USA, Europe and Asia was chaired by Professor Paul Franzon of NC State Univ and yours truly (IFTLE i.e. Phil Garrou). What makes this conference different than other conferences with 3D emphasis is the concerted effort to bring all phases of the required 3D infrastructure together including processing, design, thermal and test.

Invited keynote talks included Maaike Visser Taklo of SINTEF discussing the European eBrains program which is looking at using 3D to integrate MEMS into heterogeneous stacks for, amongst other things,  bio and medical applications. Mitsu Koyanagi updated the group on activities at Tohoku University including their spin out of Ginti [Global Integration Initiative]. Bob Patti, CTO of Tezzaron which recently acquired the old Sematech fabs in Austin updated us on Tezzaron / Novati activities and Avi Bar-Cohen of DARPA brought us up to date on the DARPA ICECool programs.

Panel Discussion on Remaining 2.5/3D Obstacles


Jan Vardaman of TechSearch moderated a panel entitled “Progress and Remaining Obstacles for 3D ICs and 2.5D HVM” which consisted of Bob Patti, CTO, Tezzaron, Prof Mitsumasa Koyanagi, Tohoku University; Dr Dimitrios Velenis, IMEC; Doug Anberg, Vice President,  Ultratech (a stepper manufacturer) and Dr Dongkai Shangguan, CEO of the  National Center for Advanced Packaging  (NCAP) in  China.

When panel members were asked about remaining material and equipment issues, Koyanagi discussed the issue of exposure tools pointing out that mask aligners did not have enough accuracy and needed very expensive 13” masks. His recommendation was i-line steppers such as Cannon.

When discussing imaging for interposers, Patti reported that interposers are by definition required to be quite large and are having trouble since current retical fields are i.e. 26 x 31mm. Anberg pointed out that in the next few years you will see 2-3X the retical field , but the cost will be more expensive optics.

Both Koyanagi and Velenis pointed out the need for better bond/debond yields and better thin die handling. Patti indicated that Tezzaron / Novati avoids that issue by doing their thinning after F2F wafer bonding so the bottom wafer becomes the carrier and is not ever removed.

All agreed that cost remains the number 1 obstacle to HVM and most agreed that improved yield and increased throughput were needed.

The interposer discussion, as with most other conferences, centered around whether silicon, glass or laminate would be the best choice. Patti offered that glass while a useful interposer material would require a major infusion of capital to get it off the ground. IFTLE as we have before, commented that glass will not enter the realm of being a real option till the flat panel display industry recognizes the opportunity and begins to address it.

Koyanagi offered that he did not see the silicon interposer market developing in Japan because the Japanese companies could not compete with TSMC.  Tohoku Univ has spun out a startup company Ginti for small volume 2.5/3D production.


GINTI, which stands for the Global Integration Initiative, has been spun out of Tohoku University with Professor Mitsu Koyanagi as CEO. With a complete line of 200 and 300mm equipment their goal is to become a one stop shop for prototype and small volume concept, design, fabrication and testing of designs that need TSV and/ or 2.5D interposers. A base-line process is set up for pilot production which is capable of using commercial / customized 2D chips.

Koyanagi (left) and Hasegawa pose with  300mm wafer of 3DIC.

Koyanagi (left) and Hasegawa pose with 300mm wafer of 3DIC.

Tezzaron / Novati

IFTLE has previously discussed the Tezzaron purchase of SVTC (former Sematech fabs in Austin) [ see IFTLE 146, “TSMC Apple Rumors; Gartner OSAT Mkt Numbers; Novati”].

During his invited presentation “A Perspective on Manufacturing 2.5/3D” CTO Bob Patti indicated that from his perspective vendors have become much more “3D aware.”

Dave Chapman and Bob Patti - Tezzaron

Dave Chapman and Bob Patti – Tezzaron

Tezaron memory technology consists of a both a controller layer and an IO layer as shown below.

Tezzaron 1

Patti reports their current capacity is 12K 300mm wafers/mo going to 26K by 2016. He announced that Novati will become a US trusted foundry later this year.

Of special interest was Bobs remark that he sees future power conversion being done on the interposer.

As an aside… Patti specifically called out new New Mexico process engineers Walter White and lab technician Jesse Pinkman as having been invaluable in both fund-raising and 3DIC process development. “Their love of Chemistry and their trust in basic Scientific principles  has brought a new enthusiasm to our whole process development team” Chapman added “…there have been several instances while walking through the fab I have actually overheard Pinkman shouting out, “Yeah  Mr. White…Yeah  SCIENCE!” His enthusiasm is contagious.

Tezz 2

For all the latest on 3DIC and advanced packaging, stay linked to IFLE.

IFTLE 165 Semicon Taiwan contd: DRAM Consolidation, Smartphone Mkt; Packaging Materials Forecast

Semicon Taiwan 2013 consisted of several programs of interest to the IC packaging community. Taking a look at the Market Trends Forum chaired by Dr Burn Lin of TSMC.

DRAM Status – Charlie Chan –  Morgan Stanley

During their discussions on the financial status of the DRAM industry, Morgan Stanley showed a great slide depicting consolidation in the DRAM memory business over the last decade.

Click to view full screen.

Click to view full screen.

Even though memory content still favors desktop/PC over tablet/smart phone the cross over point for mobile applications appears to be within the next month.

Click to view full screen.

Click to view full screen.

Smartphones – Guadois – UBS

Nicolas Gaudois Managing Director of UBS Investment Research looked at the “ The End of the High End Smartphones Run.”

UBS projects smartphones to be a maturing market with smartphone sales now > 50% of the US market. They estimate US mid to high end smartphones (> $300)  YoY unit growth of 15% in ’13E, 8% in ’14E and 5% in ’15E .

Smartphones have been the main growth engine for the semis industry out of the financial crisis. Communications accounted for 57% of TSMC revenues in 2Q13 and 51% for UMC. UBS assumes single-digit YoY revenue growth for the cellular phones industry implies similar levels for wireless semis. “This implies a longer term slowdown in semiconductor revenues growth – until more application drivers emerge.”

UBS expects to see late 2014 14nm finFET production at Intel, TSMC and Samsung.

UBS sees DRAM usage split equally between PC and mobile markets and the NAND flash demand split between mobile phones and solid state drives.

Click to view full screen.

Click to view full screen.

SEMI Packaging Materials Outlook – Dan Tracy – SEMI

The SEMI Packaging Materials forecast is shown below.

Click to view full screen.

Click to view full screen.

1. Includes PBGA, PPGA, LGA, and CSP laminate substrates and flex BGA and CSP substrates; 3. Includes die attach film (tape) materials; 4. Includes solder balls and wafer level package dielectrics

The Pacific region accounting for ~ 95% of the total market!

Click to view full screen.

Click to view full screen.

For all the latest in 3D-IC and advanced packaging, stay linked to IFTLE…

IFTLE 164 Semicon Taiwan part 2; GlobalFoundries Manocha Interview

By Garrou

Over the past few years, SEMICON Taiwan has been a conference where significant new advances in packaging technology, especially 3D-IC, have been revealed. There were no such revelations this year.

The Advanced Packaging Technology Symposium was chaired by Mike Liang, resident of Amkor Taiwan.  The 3D-IC Technology Forum and the embedded Technology Forum were chaired by Chair  Ho-Ming Tong, General Manager & Chief R&D Officer for  ASE.

FC and WLP Continue to Expand

At the Advanced packaging symposium, Vardaman of TechSearch reported that FC and WLP growth , driven by mobile products, will increase from 15% of the pie in 2012 to 21% of the pie by 2017.

TS 1

Moving to copper pillar because bump pitch is limited to ~ 130um. Cu pillar bump pitch can go to < 100um. Most are looking at NCP/NCF underfill solutions.

Corning Updates Capabilities for Glass Interposers

At the 3DIC technology symposium Shorey of Corning updated their progress in the area of glass interposers. Working on 100 to 300mm wafers and 500mm panels (100 – 700um thick) some typical results are shown below.

corning 1

Looks like current minimums at 20um TSV on 50um pitch with wafer thicknesses of 100um. Max via densities greater than 250 TSV/mm. Warpage looks better on glass than on silicon.

Click to view full screen.

Click to view full screen.

Unimicrons look at Panel Level Technology

At the Embedded Technology Forum Hu of Unimicron looked at panel level embedded technology. They offer the following comparison of WLP technology on silicon to “panel level packaging”

UM 1

(Note: IFTLE does not agree with the density capability assumptions in either category)

Two processes are evolving for embedded passive panel level processing as shown in the slide below.

UM 2

Key Process Items include (a)  Component placement accuracy; (b) Interface Adhesion with Dielectric Layer and (c) Warpage Control.

On interesting concept is the embedding of the SI interposed into the substrate as shown below. Reportedly less testing steps would be required and certainly thin wafer handling would be reduced.


Click to view full screen.

Click to view full screen.

GF’s CEO Agit Manocha on stacked die, 450mm and consolidation

Ed Spurling of Semi Manuf. & Design posted a interesting interview with GlobalFoundries CEO Agit Manocha. Manocha indicates that GF will be moving from 20 to 14nm in mid 2014 with a finfet product.

He reports that GF is working with multiple assembly houses and memory supplier partners to develop 2.5/3D technology which will be available for 28, 22 and 14nm.

He does not see 450mm being mainstream till 2020.

80% of the worlds IC production is now in moderate to high risk zones for natural disasters. GF has their production ( New York, Germany and Singapore) in the 20% low risk zone.

Moving to the 20 NAND 14 noted Manocha supports those who say there will be very few players left. He indicates TSMC, GF, Samsung and Intel. That’s it…four !

More coverage of SEMICON Taiwan is coming in the next few weeks.

For all the latest on 3D-IC and advanced packaging, stay linked to IFTLE.

IFTLE 163 Consolidation, The Leading Edge, EMPC Grenoble part 1

By Garrou

Consolidation Continues

We have spoken about consolidation many times in IFTLE. Most recently in IFTLE 148, “The Future of Packaging: A Look From 50,000 Feet” we predicted significant consolidation for both equipment and materials suppliers.  To be honest, this has been focused on the front end equipment suppliers buying up their back end brethren. What happened this week was even more significant.

The $29B merger of Applied Materials with fellow front end equipment supplier Tokyo Electron was an all-stock merger, which, if allowed by the courts, will create a global powerhouse in semiconductor and display manufacturing technology. The company will have a new name, dual headquarters in Tokyo and Santa Clara, a dual listing on the Tokyo Stock Exchange and NASDAQ, and will be incorporated in the Netherlands. Under the terms of the deal, AMAT shareholders will own 68% of the new company and TEL shareholders 32%. Tetsuro Higashi, chairman, president and CEO of TEL, will serve as chairman of the new company, while Gary Dickerson, president and CEO of AMAT, will serve as chief executive officer of the new company.

As we said in IFTLE 148, it’s all about the economics. By cutting duplicated R&D and sharing the same platforms, the companies expect to achieve $250 million in annualized run-rate operating synergies by the end of the first year, rising to $500 million in the third year.

We should not view this as “Fait accomplis” because I’m sure the antitrust paperwork is being filed as we speak by their remaining competitors.

The Leading Edge

When I started this blog as “Perspectives From the Leading Edge” back in 2008 in Semiconductor International, I noted that we would be focused on the leading edge  because “that’s where the money is made.” Further evidence of that came from IC Insights last week when they provided the headline “Leading edge technology to be responsible for entire 2013 increase in pure-play foundry sales.” [link]

It appears that 51% of TSMC’s revenue and 50% of GlobalFoundries’ sales in 2013 are expected to be from ≤45nm processing.

In 2012, only TSMC, GlobalFoundries, and UMC had significant sales of ≤45nm technology.  In 2013, TSMC is expected to have about 4x the dollar volume sales at ≤45nm as compared to GlobalFoundries and about 12x the ≤45nm sales of UMC ($10.33 billion for TSMC, $2.53 billion for GlobalFoundries, and $0.89 billion for UMC).  In contrast, SMIC only entered initial production of its 45nm technology in early 2012, more than three years after TSMC first put its 45nm process into production and is forecast to sell only $0.22 billion of ≤45nm technology this year.  In fact, only 22% of UMC’s 2013 revenue and 11% of SMIC’s 2013 sales are forecast to come from devices having ≤45nm feature sizes, which is why their revenue per wafer is so low as compared to TSMC and GlobalFoundries.

IC Insights contends that all of the increase in pure-play foundry sales in 2013 is expected to be due to ≤28nm feature size device sales. “ While the >28nm pure-play foundry market is expected to decline 3% in 2013,  leading-edge ≤28nm is forecast to triple this year.  Not only is essentially all the of pure-play foundry market growth forecast to come from leading-edge production, most of the profits that will be realized are also expected to come from the finer feature size sales.”

Click to view full screen.

Click to view full screen.

Despite continued rumors of process and yield problems in the 28nm TSMC fab, TSMC is forecast to have about $6.33 billion in sales of 28nm devices in 2013and as a result, TSMC is expected to hold a 78% share of the pure-play foundry industry’s $8.10 billion of ≤28nm sales this year.

EMPC Grenoble

The recent European Microelectronics Packaging Conference, EMPC, was held in Grenobe Fr. We will be taking a look at some of the key papers from the conference over the next few weeks.


IMEC  reported on electrical characterizations done to identify the impact of typical 3D processes on CMOS devices. They report on studies done to assess the effects induced by TSV, wafer thinning and stacking.

The Figure below shows measurements done for PFET transistors ( 2 channel lengths (50nm and 300nm) with TSV of 5um diameter). They conclude that the longer channel is more sensitive to TSV presence, i.e. at a distance of 5um from TSV center, they measure ION variation of 7% in the case of 300nm channel and 2.5% variation in case of 50nm channel. NFET transistors are less sensitive to TSV proximity. At a distance of 5um from TSV center, they measure a max ION variation of 2.5%. Similar to PFET, NFET transistors with longer channels are also more sensitive to TSV proximity.

Click to view full screen.

Click to view full screen.

No relevant change in the device drive current and therefore no major effect induced by the thinning or stacking processes.

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE.