Insights From Leading Edge

Monthly Archives: October 2015

IFTLE 259: IEEE 3DIC 2015 part 2 – DARPA , Xilinx, Tohoku Univ, IMEC/Samsung, Nikon, Chuo Univ., Torray


In his presentation “Path to 3D Heterogeneous Integration” Dan Green, DARPA program manager described their motivation for heterogeneous integration.

Modern RF systems are under pressure to make use of the spectrum in sophisticated ways, while working within limited power budgets on platforms with reduced size and weight. The compound semiconductor (CS) electronics industry is well-positioned to address these challenges, due to the superior properties and diversity of CS materials. For example, high electron mobility and peak velocity of InP-based material systems have resulted in transistors with fmax above 1THz . Wide energy bandgap GaN has enabled large voltage swings as well as high breakdown voltage RF power devices. The excellent thermal conductivity of SiC makes tens of kW power switches possible. On-chip high-Q micro-electromechanical resonators and switches in materials such as AlN, have been demonstrated that potentially can be used for clock references and frequency selective filters.

The DARPA view is that the future of CS electronics depends not on displacing Si, but rather on heterogeneous integration of compound semiconductors with silicon technology in a way that will allow the advantages of the two technology types to be optimally combined.

The DAHI Foundry Technology thrust was initiated in 2013 to advance the diversity of heterogeneous device and materials available in a silicon-based platform and make this technology available to the greater DoD and commercial microsystems design community through the establishment of an accessible, manufacturable foundry offering for device-level heterogeneous integration. Recently, a DAHI multi-project wafer run was demonstrated utilizing 0.25um InP HBTs, 0.2um GaN HEMTs heterogeneously integrated with 65nm Si CMOS. A chiplet assembly approach was chosen as the primary path at the DAHI Principal Foundry because of reported advantages in flexibility and processing of dissimilar materials.


Xilinx updated the audience on their 2.5D FPGA program. Xilinx has participated since 2006 in 3D-IC technology development. Today there are more than (7) 3D-IC products from 2 generations of FPGA family nodes in shipping to customers. The figure below compares the different technologies available for high density interconnect.

IFTLE259_Fig1 Tohoku Univ

Rittinon and co-workers reported on the stability of electroplated copper thin film interconnect.

The mechanical properties of electroplated copper thin films, such as Young’s modulus and tensile strength vary drastically compared to those of conventional bulk copper. The reason for the variation and fluctuation of these mechanical properties is that the electroplated copper thin films mainly consist of fine columnar grains with porous grain boundaries as shown in the figure below. This micro texture changes the mechanical properties of the electroplated copper thin films significantly from those of bulk copper.

IFTLE259_Fig2The existence of porous grain boundaries is the main reason for the high resistivity and local high Joule heating in the electroplated copper interconnections. Therefore, the crystallinity of the electroplated copper thin-film interconnection has significant effect on the long-term reliability of the interconnections. They find that high Joule heating appears at grain boundaries with low crystallinity.

It is well-known that the crystallinity of electroplated copper interconnections is improved by high temp annealing. Since recrystallization and/or grain coarsening occurs during annealing, however, high tensile stress remains in the annealed interconnection because the shrinkage of the film is strictly prohibited by the surrounding silicon in a TSV structure. Such high tensile stress is the main reason for stress-induced migration in the interconnection resulting in the formation of a lot of voids in it.

Since the lattice mismatch between tantalum (the Cu migration barrier layer) and copper is about 18%, these researchers feel it is necessary to introduce an intermediate layer as the seed layer material between them. They report that a thin layer of ruthenium is an effective material for minimizing the lattice mismatch. It decrease the lattice mismatch from 18% to 6% thus lowering the overall stress formation.


It has been known for several decades that low temp oxide wafer bonding can be enhanced by plasma treatment of the oxide surfaces by process flows such as the one shown below.

IFTLE259_Fig3Researchers at IMEC and Samsung have now studied the potential for low temp bonding by dielectric films other than SiO2. The figure below shows the results of the surface roughness and bond strength measurements for SiOx, SiOxNy and SiCxNy surfaces that were treated with O2, Ar or N2 plasmas. Among those three dielectric films, the SiCxNy film had the best bonding strength in the same low temperature annealing condition for 2h at 250°C.



Sugaya and co-workers reported on a new “precision” wafer bonding technology for 3DIC. The technology includes a new precision alignment methodology and a unique thermo-compression bonding procedure. Experimental results show that the alignment capability is 100nm or better, and permanent bonding accuracy of 260 nm (|mean| + 3σ) in 300 mm Cu wafer bonding.

Chuo Univ.

3D memory with TSV has been proposed as a candidate for the next generation integrated solid-state drive (SSD) with storage class memory (SCM). Such a 3D-TSV SSD is expected to have advantages of fast speed, low power consumption, and high endurance. The table below summarizes the comparison of simulated write performance, energy and required minimum I/O data rates by using the SSDs with and without 3D-TSV. The write energy reduces 68% by applying 3D-TSV in the SCM/MLC NAND hybrid SSD.


Toray has examined increasing the productivity of IC stacking by thermos compression by a “collective” process as shown below.

IFTLE259_Fig6When NCF is used with TCB, enhancement of productivity is an important issue, because it takes about 10 sec to cure the NCF and at the same time melt a solder and connect to an electrode on the substrate. They propose one technique to solve the problem, is by using “collective bonding”. In a pre bonding process, chips are placed quickly at low temperature. Pre bonding of the four layer on a Si substrate was performed in the condition that the stage temperature is 80°C and the head temperature is 150°C for 0.8 s. Post bonding was performed by the equipment which has an improved stage for 3D stacking. As the post bonding condition, the peak temperature of second step of bonding head was set to 280oC so that the temperature in the NCF of the lowest layer was 240°C which was enough to melt a solder. The stage temperature was set to 80°C.

Another technique to speed up the overall process is gang bonding where several chips are placed onto the substrate and bonded at one time.


For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…


IFTLE 258: IEEE 3DIC Sendai Japan; GINTI

By Dr. Phil Garrou, Contributing Editor

The official IEEE 3DIC meeting started in 2009. It rotates from the USA to Europe to Asia on an annual basis. I say official because we all know that “3DIC” has been a buzzword, so every electronics conference in the world has sought 3DIC content, including competing IEEE conferences.

This year’s conference was in Sendai Japan and headed up by Mitsu Koyanagi from Tohoku University. Many of you may not know that Koyanagi-san is viewed as one of the fathers of 3DIC based on his early work in the late 1980s, such as his famous paper “Roadblocks to Achieving Three Dimensional LSI”. He has been working on the three key technologies for 3DIC (thinning, TSV, and bonding) since that time. He will be receiving a “Pioneering Award” for his 3DIC activities this fall at the 3D ASIP Conference which I will be chairing. [Link]


IFTLE has discussed GINTI previously (see IFTLE 166, “IEEE 3DIC Conf part 1; 3DIC panel discussion; Ginti; Novati”).

One of the plenary presentations at this year’s IEEE 3DIC conference was “Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University” by KW Lee, Koyanagi-san, and co-workers, detailing the activities at the University and the prototyping spin-out.

The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the R&D of 2.5D/3D integration technologies and applications. GINTI provides a process development infrastructure in a manufacturing-like fab environment and “low cost”, prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process. The figure below shows their 8/12-inch 2.5D/3D integration process equipment

State-of-the technologies include design, layout and mask making to wafer thinning, forming of TSV on chip/wafer (front side/backside TSV), redistribution routing, both side micro-bump formation, chip/wafer stacking, failure analysis, and reliability testing.

GINTI can provide 3D prototype LSI stacking using commercial 2D chips by die-level 3D hetero-integration, backside TSV formation and various stacking (C2C C2W, W2W, and self-assembly) technologies.

IFTLE258_Fig1GINTI mainly focuses on via-last backside TSV approach, because they feel it is a better solution for heterogeneously integrating different function, size, and material devices, with better flexibility for commercial chip/wafers.

Their process flow for via-last backside TSV fabrication is shown below. The incoming LSI device wafer with metal bumps is temporarily bonded onto a support wafer. Then the Si substrate is thinned to target thickness from the backside by grinding and CMP. After via patterning on the ground surface, the deep Si trench is formed from the backside by RIE processing until the first level metallization layer (M1) is exposed. Oxide liner is deposited via holes and the bottom oxide liner in via hole is selectively etched by dry etching to re-expose the M1 layer. Next, the deep trench is filled with Cu by electroplating after dep of barrier and seed metal layers. Re-distribution layer (RDL) is then formed on the backside and metal bumps are formed on the RDL by electroplating. Finally, the support wafer is de-bonded from the thinned LSI wafer.

IFTLE258_Fig2To create new 3D hetero-integrated systems, they have developed die-level 3D integration technology as shown below. Commercially available 2D chips with different functions and sizes, such as those of sensor, logic, and memories which were fabricated by different technologies, are processed to form TSVs and metal micro-bumps and integrated to form a 3D stacked chip in die level.

IFTLE258_Fig3The image below shows a 3D stacked image sensor chip comprising three layers of CIS, CDS, and ADC chips for high-speed image sensor systems.

IFTLE258_Fig4For all he latest on 3DIC and other advanced IC packaging solutions stay linked to IFTLE…

IFTLE 257: IC Insights’ McClean Report Forecast Revisions

By Dr. Phil Garrou, Contributing Editor

IC Insights’ fall revisions to the 2015 Forecast

For nearly two decades, the industry has eagerly awaited the yearly release (early in the first quarter of each year) of the so called “McClean report” issued by IC Insights, which documents and projects the status of our industry.

A fall forecast seminar was just held in Sunnyvale detailing how global economic conditions and emerging developments have reshaped sales forecasts unit shipments and pricing trends for the balance of the year through 2019.

The major message was that semiconductor industry growth, initially pegged at 7% at the beginning of the year, will be closer to 2% and will rise only 4.9% on a compound basis by 2019 to $450B.

Although IC unit sales are expected to increase ~6%,  ASP are falling ~5%, leaving the market flat.

Although IC unit sales are expected to increase ~6%, ASP are falling ~5%, leaving the market flat.

We are basically mimicking the GDP, which is what market segments do when they are mature. And recall IFTLE has been telling you that most market segments are now late in category 3 or already in category 4 (mature).

McClean was quoted by EE Times as saying: “We won’t have a big cycle in semiconductors till there is a big cycle in GDP growth, and it doesn’t seem like its coming” adding that “In general IoT doesn’t look like the savior for returning this industry to 10% growth rates…something could hit with tremendous impact very quickly … [but] the world’s still looking for the next big thing in technology,” and when discussing 450mm wafers, “Five years ago I was 95% sure it would happen in about five years, now its 50/50 whether it happens at all.

Their new assessment of top growing IC Markets is shown below:

IFTLE257_TableWhen looking at the next gen logic/foundry process roadmaps, McClean points out that Intel has just pushed out the 10nm node to 2017.

IFTLE257_Fig2IFTLE has noted several times that the money is made on the leading edge and that’s the main reason to make sure you are keeping up. Well McClean’s latest plot of TSMC’s revenue ramp shows this is spades. At the 45 node it took eight quarters to achieve 20% of total sales, five quarters at the 28 node, and just three quarters at the 20 node.

IFTLE257_Fig3For all the latest in 3DIC and other advanced packaging stay linked to IFTLE…

IFTLE 256: Semicon Taiwan part 3 – substrate and panel processing by Unimicron, Fraunhoffer IZM & J Devices

By Dr. Phil Garrou, Contributing Editor

This week lets finish our look at the substrate and panel level processing activities at Semicon Taiwan 2015’s Embedded and Wafer Level Package Technology Forum.


DC Hu reviewed Innovative Substrate Technologies including glass as a candidate material for high density substrates and interposers.

When it comes to the impact of panel level processing on the cost of high density substrates most would agree that while large glass and PCB panels are available at a reasonable cost, it is not yet clear that current equipment can produce the required densities and thus meet the low cost expectations. Never the less, it is certainly worth the effort to develop the data and sort this issue out.

IFTLE256_Fig1For glass, one of the main questions has been can you make electrically and mechanically functional vias and fill them with conductive metals. Hu compares the current via forming capability of Va Mechanic, LPKF and Corning as is shown below. It appears that the most advanced systems are currently developing < 100um glass thickness, ~25um holes at a throughput of > 2000 holes/sec.


Laser & Electronics AG (LPKF) is a German equipment manufacturer that focuses mainly on PCB prototyping and micromachining solutions for SMT stencils. Via Mechanics, previously known as Hitachi via mechanics Ltd has been engaged in manufacturing, printed wiring board (PWB) manufacturing systems.

Unimoicron is also developing a laminate using glass as core as shown below. Glass has a 3X better flatness (R < 0.5mm) than an organic core given he same core CTE (i.e. 3 ppm/°C). Such technology is currently being demonstrated at 508 x 508mm; 100-200um glass thickness; with 8/8um L/S on ABF dielectric.


They have demonstrated sub 2/2 L/S on test vehicles.

Fraunhoffer IZM

Tanja Braun and co-workers at IZM/TUB detailed their studies on fan out panel level processing. They listed the following as the most obvious challenges:

IFTLE256_Fig4The equipment they have put in place for ~600 x 450 panel level processing line is shown below.


J Devices Panel Level Processing (PLP)

Reasons for wanting to develop pane level processing are obvious. A 500 x 400mm panel has 3X the area of a 300mm wafer.

IFTLE256_Fig6The standard PLP process flow is shown below:


J Devices is equipping a PCB facility to manufacture the PLP technology.

J Devices makes the point that required RDL technology depends on the application. For example Application processors require wafer photolithography while modules for RF/PMIC only require PCB photolithography.

For all the latest on 3DIC and other advanced packaging stay linked to IFTLE…