Insights From Leading Edge

Monthly Archives: November 2010

IFTLE 25 IMAPS Part 2 Advanced Packaging

IBM Going Fab Lite ??

Peter Clarke of EE Times is reporting that “ â??¦ IBM appears set to gradually back away from semiconductor manufacturing and to rely for its leading-edge silicon on Samsung and GlobalFoundries as foundry suppliers (link). If you are a reader of IFTLE you already knew that [ see IFTLE 8 "3D Infrastructure Announcements and Rumors”, July 2010]

“â??¦ IBM is gradually allowing itself to exit from leading-edge manufacturing at high volume. IBM appears to have joined the broad class of semiconductor companies that will never build a major wafer fab again” reports Clarke. Interestingly the last time that IBM was close to the global top 10 was in 204 when they ranked 11th.

Several Govt. types were shocked when I shared this rumor a few months ago. Clearly they shouldn’t have been. It appears that such business decisions will take what remains of IBM manufacturing prowess the way of Bell Labs, DEC and many of the other early giants in our USA microelectronics industry..

Advanced Packaging at IMAPS National

IBM Injection Molded Solder

IMS is a variation of C4NP for solder deposition on fine-pitch laminates.

The presentation on this technology is examined in detail in the ElectroIQ advanced packaging section by the presenter Jae-Woong Nah [link]: 


Alan Huffman of RTI Int presented an overview of the evolution, status and possible future for bumping /WLP which I co-authored. RTI, as you know, purchased the Microelectronics Center of NC (MCNC) ~ 4 years ago. MCNC spun off Unitive which is now owned by Amkor but “back in the day” bumping pioneers such as Iwona Turlik, Dan Mis, Glenn Rinne, Paul MaGill, Phil Deane, CJ Berry, Ted Tessier, Boyd Rogers and many others developed a plated bump process that is still used globally today. In fact the joint industry standard on “implementation of flip chip and chip scale technology” put out in 1996 by EIA/IPC/JEDEC/SEMATECH/MCNC was put together at a meeting on the MCNC campus.

Historically flip chip (or C4 as IBM called it) had been around since the 1960s but things took off commercially in 1992 after Tsukada of IBM Japan announced that they had discovered that the use of underfill allowed reliable joints directly to PCBs (i.e chip-on-board). After the commercial use of flip chip in the Motorola StarTac cell phone in 1996 the commercial use of flip chip in consumer products exploded.

It is clear today that flip chip and WLP are evolving into copper pillar bump (lower electrical resistance and inductance; lower thermal resistance; better resistance to electromigration; reduced pitch) and WL fan-out packaging (allows more IO at same pitch). A complete description of Huffmans presentation is given in a podcast interview with SST Editor Debra Vogler which can be accessed here [link].

Micron’s presentation on the next generation of PoP (package on package) indicated that there would be a required reduction in Z height of the top memory package. This in turn will require reducing die thickness and reducing the mold cap thickness.

While transfer molding is the standard mold method used in the semiconductor industry, this method has limitations when it comes to very low mold cap clearance. Issues include mold voids, bond wire sweep, and filler segregation.

Compression molding has been introduced in fan-out WLP for full wafer molding. Micron now reports that compression molding of PoP top memory packages is the most suitable molding method for structures with reduced mold cap thickness.

A key parameter for PoP packages is the warpage during reflow. Shadow Moiré was used for measuring package warpage. The study found that compression molding and transfer molding yielded equivalent package warpage when using the granular forms of mold compounds. For top PoP packages that tend to have thin mold caps, Micron reports that it is necessary to choose a mold compound with lower coefficient of thermal expansion CTE1 (below Tg) and CTE2 (above Tg) and lower cure shrinkage.

Finite element simulations indicated that the coplanarity, as well as warpage of small size packages (12mm x 12mm and below), could be controlled to under 100 μm.


We have recently reported on NEPES licensing of the Freeescale RCP (redistributed chip package) technology for fan out packaging [ see IFTLE 2, “Advanced Packaging at the 2010 Las Vegas ECTC”, June 2010].

At the IMAPS National meeting NEPES took another major step in advanced packaging when they revealed the details of their silicon module (SiP) program silicon module with Cu filled TSV and IPD (integrated passive device) LPF (Low band pass filter) integrated at the surface of silicon interposer as shown below.

The 7 mm x 7 mm Si interposer is 200 um thick. The entire package is limited to < .8 mm thickness. The spiral inductor is formed in the backside RDL layers from 8 um ED copper in low K polymer. MIM capacitors are fabricate by Al/SiO2 front end TF (thin film) processes and Cu/polymer back end processes.
The LPF shown below is fabricated from two inductors of 2.508nH, one inductor of 5.24nH and two capacitors of 1.641pF fabricated by front-end Al/SiO2.

For all the latest in 3D IC integration and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦.

IFTLE 24 IMAPS National Summary Part 1 – 3D Highlights

The IMAPS USA annual or “National”, as it is known, was held in Raleigh a few weeks ago. Rajen Chanchani of Sandia National Labs took over the helm as IMAPS President during this meeting with long time industry stalwart Voya Markovich next in line. Rajen’s name should be familiar to all packaging practitioners since he was part of the team that developed the Sandia mini BGA back in 1997 [see “Mini Ball Grid Aray Assembly on MCM-L Boards”, ECTC 1997] which WLP historians like Peter Elenius and yours truly credit as the first WLP structure. Voya, all of you know for his decades long development of high density PWB solutions such as “film redistribution layer technology” at IBM and subsequently Endicott Interconnect . The photo below shows the assemblage of past IMAPS presidents that were at the Raleigh meeting.

Meeting General Chair was Dave Seeger who at the time he signed up was on loan to SRC here in the Research Triangle, but since has moved back to IBM in NY. Technical Chair was Sara Paisner from Lord which is headquartered here in the RTP area.

This years meeting had a significant 3D focus with several professional development courses and 5 sessions which included a panel session on “Roadmaps, Technical and Business Progress” We’ll first take a look at 3D and in the next blog look at other topics in in advanced packaging.

3D IC Panel session

The 3D panel session was headed up by RPI Professor James Lu, panelists are shown below:

IMAPS 3D Panel: Phil Garrou (Microelecttronic Consultants of NC); Nick Sillon ( Group Manager, CEA Leti); Klaus Hummler ( Sr Principal Engineer, Sematech); Urmi Ray ( Sr staff engineer, Qualcomm); James Lu (Professor RPI); Rozalia Beica (Program Director, EMC3D); Dorota Temple ( Program Director, RTI)

When asked about the 3D commercial timeline I commented that roadmaps of many companies (TSMC, UMC, Elpida, ASE etc.) now appeared in sinc and all point towards commercialization in the 2011-2012 timeframe. Ray commented that Qualcomm, a very public supporter of 3D IC technology , sees “two years out (2012)” as “about right”. Hummler was a little more hesitant about timing indicating that “â??¦Nokia is pointing towards product introduction in 2013 but we believe this will be a stretch”. Beica indicated that 15 3D lines were going in place across the world (I assume this included commercial, university and institute lines)

When asked about standards, Ray, herself involved in several standards initiatives, pleaded for more work on standards “now”. Hummler commented that for fables companies standards are a “matter of survival” .

When questioned on the role of consortia and institutes, Sillon responded that “â??¦the role of consortia is to show demonstrators of what can be done with 3D” .

Temple reminded the audience that 3D allows “.. separating digital from analog layers which results in lower power product developments” She also pointed out that we may need what she called “Second generation OSATS” which would be skilled in “..processing not usually done by the OSATS today”.


As we have noted in the past Sematech’s role in the 3D IC infrastructure is to">drive convergence of the materials/equipment solutions by:
– creating roadmaps and standards
– working with others including Member Companies to drive convergence
– industry consensus building through workshops and forums

Klaus Hummler, who has recently moved to the Sematech Interconnect program from siXis, discussed their technical focus area namely “Via-middle” ( TSV’s formed after FEOL and before BEOL) with the following attributes:

• TSV before 3D stacking
• Wafer thinning before 3D stacking
• Back-to-face bonding
• Die to wafer bonding
• TSV diameter 5 μm
• TSV pitch 10-50um
• 20-50 μm TSV depth

Long time readers will note that this is exactly where IFTLE (and PFTLE) has been pointing you for the past 3 years.

EMC-3D / Applied

The name Rozalia Beica has become synonymous with 3D IC in the past few years. Rozalia has been one of the “faces” of the EMC3D consortium [ see PFTLE 47, “3D IC Questions and Answers from the EMC-3D Consortium” After the acquisition of Semitool by Applied Rozalia rejoined the Semitool business unit of Applied Materials working in their 3D program. Processes supported by EMC3D are shown below:

Applied has put together a lineup of tools to address TSV fabrication as shown below (sorry for the small print). Beica reports that Applied, at their Mayden Development center 3D line have  run more than 50 integrated demos.

Beica reported that their newer via fill processes show a 50% reduction in overburden and significantly purer copper which results in significantly less Cu extrusion (Cu pumping) and micro voiding.
Paul Enquist, CTO of Ziptronix reports that their direct bond oxide technology catching on with fabricators of backside illuminated CMOS image sensors.  Enquist also shared the first released cross sections of a 10 µm pitch, 463,000 connection daisy chain built with the Ziptronix DBI process with Cu filled TSV fully protected by barrier layers (below). Enquist reported a 99.999% yield on such structures.

John Lannon, Sr engineer at RTI Int described the RTI bonding process developments. He warned the audience of electrical failures during reliability testing of 3D test vehicles bonded with Cu/Sn/Cu intermetallics, “â??¦the yield goes to zero after 96 hours standard autoclave testing” Lannon added “ â??¦standard epoxy underfills do not seem to solve the problem, but we have found a silicon underfill that allows device survival through the autoclave testing. More work is needed to completely understand this issue and all potential solutions“ An interesting dialog occurred during the question and answer period of Lannons presentation. An unknown questioner from the back of the room stated that Cu/Sn/Cu bonding used by so many of today’s 3D IC practitioners was nothing more than copper pillar bonding and that (paraphrasing) “â??¦copper pillar bonding is patented by APS and anyone practicing this technology must be licensed by APS”. APS is of course Avanpack in Singapore and indeed I am aware that Amkor, Unisem and Flip Chip Inc have taken out such licenses. I do not support or reject the questioners statement without further study (yes – I do serve as an expert witness !) but I certainly do bring it to your attention.

Rhett Davis, Professor of EE at NC State showed much od the work that he and fellow Professor Paul Franzon have been doing in the 3D area. 3D specific designs were shown that achieved 65% power reduction and an 800% increase in memory bandwidth.

Jeremy McCutcheon of Brewer Science reviewed their Zonebond process (link) showing the audience significant details on the carrier removal step once the wafer is laminated to a film frame. McCutcheon warns that “â??¦ solvent strip on film frame an issue since some solvents attack the glue on the film frame. This step must be done properly”

Between now and the end of the year IFTLE will be looking at:

– Napa KGD conference
– IEEE 3D Test workshop

– RTI 3D ASIP Conf
…as well as any and all announcements and rumors that you need to be aware of.


The RTI ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) will be held in Burlingame CA on Dec 8-10. 3-D ASIP is focused on technology advancements, business issues and infrastructure development. Among the many invited speakers are Erik Volkernik CTO of Verigy, Subramanian Iyer of IBM, Doug Yu of TSMC, Ho-Ming Tong of ASE, Bob Patti of Tezzaron, Arif Rahman of Xilinx, Marc Scannell of Leti, Bob Lanzone of Amkor and many, many other industry experts. Hope to see you there.

For all the latest in 3D IC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦.

IFTLE 23 Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor and Intel Looking at Foundry Options

Took a little time off to have Halloween with grandaughters Hannah and Madeline in Houston. If you’re a kid in America what a great holiday Halloween is.  Basically, strangers give you candy for dressing up and pretending to be someone or something your not. Hummmâ??¦come to think of it, this is a bit like politics where politicians pretend to be something their usually not (honorable, honest, concerned ) when really all their after is the candy. When it comes to trick-or-treat we are usually the ones who are tricked. Well that’s a discussion for another day. Hannah (6) and Madeline (2) certainly had a great time as you can see below.
Xilinx 28 nm FPGA will use Si Interposer

The true 3D aficionado has been waiting for the first true commercial product announcement. We already have face to face stacking without TSV (chip-on-chip in the Sony Playstation and many other products) and TSV being used for 1 layer image sensors (nearly all of todays CMOS image sensor manufacturers) but when will we see a true 3D design which will contain (a) TSV, (b) stacking and (c) thinning ?

We were teased this past week with headlines such as “Xilinx Stacked Silicon Interconnect Extends FPGA Technology to Deliver ‘More than Moore’ Density, Bandwidth and Power Efficiency”. I must acknowledge that it does not directly say anything about 3D, but there certainly was a lot of buzz in the industry since the packages make use of TSV interposers.

We have seen a lot of structures recently that use the silicon interposer to mate die to the top and bottom of the interposer (i.e the Renesas SMAFTI) . Last week Xilinx announced a single layer, multi chip silicon interposer for its 28nm 7 series FPGAs. These FPGAs reportedly extend the range of applications programmable logic can address by offering up to 2 million logic cells for high levels of computational performance and high bandwidth.

The 28nm Virtex-7 LX2000Tmulti die FPGA will provide more than 3.5X the logic for capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers.

Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid any thermal and/or design issues that would be introduced had a pure 3D IC vertical die-stacking approach been taken. This will reduce power, and improve performance compared to a multi-FPGA approach

Xilinx reports that they have been working with TSMC and their assembly house Amkor. The device is made possible by Amkors micro-bump assembly, FPGA architectural innovations from Xilinx, and advanced technology from TSMC. The new products deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.

By using TSV silicon interposer to implement their stacked silicon interconnect approach, Xilinx reported that they “ reduced the risk involved with thermal and design issues of full 3D IC stacking” This probably means that full 3D just is not ready yet and we will be seeing more ”Xilinx like” designs in the near future before we see full 3D in a few years from now.

According to Xilinx, Initial devices will be available in H2 2011.

For more technical information including white papers, visit the Xilinx web page at:

Amkor /TI Copper Pillar Technology

The week before Semicon West Amkor and TI announced that they had qualified and begun production of the industry’s first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to current solder bump flip chip technology [link]

Very little follow up was available because of the exclusivity TI was given as part of the joint development program. The publically available data left me once again asking “Where’s the Beef” [ see IFTLE 3 "â??¦on finding the beef and finally addressing 3D IC"]

I was personally told that full technical details are being withheld till the next ECTC conference [ June 2011].

Last week Amkor did release come details on their technology. For all the available information on this technology see the amkor website here (AMKOR) .Design rules are shown below.

The Weibul plot shown below shows an improvement in life for Copper Cu pillar over SnAg bump for the same current / temperature condition and similar bump / UBM geometry. No failure was observed in Cu Pillar Bump even after 8000 hours of testing at the same condition.
Fellow blogger Dick James has done some reverse engineering which can be found here (link).[added 11/09/2010]
Intel Becoming a Foundry ??

Intel has agreed to manufacture a specialized microprocessor design for Achronix Semiconductor at its most advanced factory [link]. While the production use less than 1% of Intels production capacity, it certainly is a departure from their normal business model and may point to their experimenting in the foundry business to keep such options open for the future. While Intel is brushing this off as non important, I would kep an eye out for similar developments.

For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦.