Insights From Leading Edge

Monthly Archives: November 2011

IFTLE 77: MEPTEC 2.5, 3D and beyond

Last week in Silicon Valley MEPTEC and Semi held the "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference.

Zeki Celik, principal engineer in the package design and characterization group at LSI, looked at the thermal characterization of various 2.5 and 3D package configurations. Option 3, where the logic die is not heat sinked to the lid, results in the overall highest TJ, max. Option 2, where the silicon interposer is between the memory and the logic die, can be heat sinked to the lid lowers the overall temperature, but equilibrates the temperature of the memory to the temp of the logic. Option 1, which is the silicon MCM-D option, is the overall best solution with the lowest memory temperature.

Marnie Mattei, senior director of TSV product development at Amkor Technology, examined assembly strategies for interposed products. Primary drivers for interposers, which are now pretty much stansdardized at 100μm thick, are shown below.

Product challenges include:

Die-die / Die-substrate joining
– Micro bump uniformity; method of join; materials

Die-die X-Y spacing
– Fillet sizes and pad metallurgy
– Process assy sequence; micro-join method & materials

Thermal / power management
– Use of lids, stiffeners & passives
– Underfill/resin bleed, adhesive compatibility
– Process assy sequence; micro-join method & materials

Warpage control
– Interposer warpage; substrate warpage
– Top die warpage — top die area density/distribution

Intermediate e-test points
– Process assembly sequence

Available assembly flows in Amkor include:

[tc=thermocompression, NCP=non conductive paste (preapplied underfill); CUF capillary underfill]

Sunil Patel, director of GlobalFoundries’ customer package technology group, looked at backside integration and global supply chain challenges for 2.5 and 3D. He sees some application segregation as follows:

GF’s perspective on supply chain options mimics many others, namely foundry-centric, OSAT-centric, and 3rd party-centric.

Although GF pointed towards many collaborations with customers, OSATs and institutes, no indication was given as to when and how to expect GF to begin volume manufacturing of 2.5 or 3D products. While others have recently proposed that GF manufacturing is imminent, IFTLE does not see this happening just yet; they are probably still a year or two away.

Subramanian S. Iyer is an IBM Fellow and chief technologist at the microelectronics division within IBM Systems & Technology Group, responsible for technology strategy and competitiveness, and functionally for embedded memory and three-dimensional integration. His presentation focused on prospects for 2.5 & 3D integration. Among his main messages:

– Scaling is getting more difficult and expensive and yielding less;
– Bandwidth and latency are at a premium;
– Power management, delivery, distribution, and dissipation are significant;
– Integrating large amounts of low latency memory is a major challenge for modern multi-core processor design;
– 3D achieves high performance and low power (AC); and
– Supply chain management will be the toughest nut to crack

Repeating a theme that Subu has shared at previous conferences, he showed the cross-section of an 11-level-metal, 32nm chip (below) to make the point that due to size miss match, sometimes vias-middle TSV must be connected at upper levels of metal and not at the lowest level as we usually draw them in our cartoons.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE………………….

IFTLE 76: Advanced Packaging at IMAPS 2011, recent 3D announcements

Finishing off our look at IMAPS 2011, we will examine some of the advanced packaging presentations.


PDMS stamps have found a lot of use recently as stamps for soft lithography. NuSil, maker of high purity silicones gave an interesting presentation on PDMS (polydimethylsiloxane). Evidently there are impurities in the PDMS that must be removed to produce a low outgassing product (required for space use), and fillers can be added to adjust its natural mechanical properties.

Specialty Coating Systems gave a presentation on their Parylene (xylylene polymers) CVD polymer product line which can be used as chemically inert barrier layers. Of special interest were the properties of Parylene HT which shows resistance toward thermal and or oxidative degredation up to 450°C and its UV resistance makes it a candidate for use as a protective layer for LED devices.

Daetec has looked at PBI (polybenzimidazole) as a temporary bonding material due to its properties of high thermal resistance, low outgassing and low stress.

Freescale reported on the adhesion of molding compound to SiN and SiON passivation surfaces. Both passivation surfaces were treated with O2/Ar plasma prior to the molding process. It is found that the SiN surface performed better than SiON electrically without showing any delamination for the mold compound studied. Both passivation surfaces were analyzed by TOF-SIMS immediately before and after the pre mold plasma treatment. The major observed difference was in OH group intensity. OH is increased on the SiN surface after plasma treatment while it is decreased on the SiON surface after treatment. It is inferred that the presence of OH group enhances the mold compound adhesion.

Kaist has studied the suppression of Kirkendall void formation in Sn/3.5Ag /Cu solder joints by pre-annealing. Pre annealing electroplated copper at 500-600°C for 2 hrs significantly suppresses Kirkendall void formation in the Sn-3.5Ag/Cu solder joints. Grain growth was observed as anneal time and temperature increased. SIMS analysis shows the annealed Copper films contained less C and S impurities.

Pac Tech has examined "Wafer level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm " [PDF link]. They have examined placing solderballs by both WLSST (Wafer Level Solder Sphere Transfer) shown below and SB2 (solder sphere jetting)

For WLSST 40μm solder balls were successfully placed while balls < 40μm were not — because such placement requires a stencil with 15μm openings and no stencil manufacturers can deliver such a stencil today.

Solder jetting with 30μm SnAg3Cu0.5 solder balls was successful, although such small balls of other solder compositions were difficult to obtain from suppliers. Underfill processes for flip chips with 30μm and 40μm solderballs were developed. Reliability was tested according to MIL 883G — 8000 temp cycles between -55 and +125°C were passed.

Recent announcements in the 3D infrastructure

EV Group, IZM-ASSID JDA to develop chip-to-wafer temporary bonding

Upgrading 3D wafer level technologies to 300mm wafer size is the next step in effectively assisting leading companies in meeting the requirements of their future products. The ASSID (All Silicon System Integration Dresden), part of the Fraunhofer IZM Berlin, was established to meet this specific challenge. [see PFTLE 74: "All Silicon System Integration Dresden (ASSID) — A 300mm 3D IC line for Germany"]

As part of this program, ASSID and EVG have announced an agreement to jointly develop high-volume temporary bonding and debonding processes to support chip-to-wafer bonding manufacturing processes for 3D IC integration applications. The joint-development project will take place in ASSID’s facility in Dresden. Process development work will be accomplished using EVG850 TB/DB systems already installed at Fraunhofer IZM-ASSID’s facility.

Brewer Science and EV Group come to agreement on ZoneBOND

The recent announcement by Brewer Science and EVG [see: Brewer Science, EVG commercialize temporary wafer bonding with zoning laws] means the IP issues between the two parties have been settled and the technology can move forward. ZoneBOND defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone. Therefore, only low separation force is required for carrier separation once the polymeric edge adhesive has been removed by solvent dissolution or other means. [see IFTLE 61: "Suss 3D Workshop at Semicon West"]

Numerous major players were intrigued by the technology but have been awaiting this resolution before they move forward.

In a linked announcement, EVG announced temporary bonding /debonding) equipment modules that support ZoneBOND technology [link]. It is interesting that EVG has opened its equipment platform to "enable the use of a wide range of adhesives from various suppliers to give customers the most flexible choice of bonding materials." This can be interpreted as meaning that they are no longer as closely wed to the Brewer product line as they once were, a position previously adopted by their competitor Suss Microtec.

Invensas aquires Allvia patent portfolio

Invensas, a wholly owned subsidiary of Tessera, has acquired the patent portfolio of Allvia and agreed to a two-year collaborative partnership to "further develop technology and IP in the 3D space".

The 64 patent portfolio consists mainly of technologies and processing dealing with "silicon interposers, TSV and micro bumping for wide IO mobile and 3DS DRAM."

While it certainly makes sense for Allvia to turn over the IP side of its business to Invensas and focus on foundry manufacturing for customers (including Invensas), it is certainly interesting that Invensas, whose stated corporate goals are to "acquire, develop and monetize strategic intellectual property" agreed to Allvia retaining a "back license" to offer the IP to other customers as was reported [link].

IFTLE interprets those comments as meaning they are offering the products, not licenses to the IP, but we may be wrong.

For all the latest in 3D IC and advanced packaging stay linked to IFTLE……….

Hope to see many of you at the RTI ASIP [ Architectures for Semiconductor Integration and Packaging] Dec 12-14!

IFTLE 75: LED market is about to explode

IFTLE 75 is a nice round number and if we combine these with their predecessor PFTLE (still accessible here) we are now past 200 and approaching four full years of these weekly updates. Certainly no other information source available has been following 3D IC on a weekly basis for as long. I’ll try to come up with something special for IFTLE 81, which would be the beginning of Year Five.

Once again I thank all of you, my readership, for paying attention. Hopefully there continues to be something for each of you to learn from each and every blog.

We’ve spent a lot of time the last four years discussing what’s going on in the 3D IC space because undergoing this evolution some day will be viewed as a very important event in IC packaging history. But that doesn’t mean that there are no other very significant packaging evolutions and market opportunities going on at the same time. Certainly the LED space is one of those.

We all know that LED producers are looking at white light and replacement of the incandescent bulb as the "big dog" driver application in this space, and I have ranted on the demise of "Lester the Lightbulb" [see IFTLE 63: "Bidding Adieu to Lester Lightbulb"].

Yole Développement and IC Insights have both released recently some very interesting LED component and packaging market data. The overall LED marketplace according to Yole looks something like this:

Further, Yole’s LED experts expect all phases of LED production, including packaging, to undergo a >10Ã?? cost reduction over the next 10 years.

It is an IFTLE perception that backlighting for TVs will be equally, if not more important than home lighting.

LED-backlit TVs and smart televisions which allow consumers to browse and view shows directly from the Internet, have replaced 3D TV as the "must-have" features driving television purchases in 2011, according to the soon-to-be-released 2012 edition of IC Insights’ Integrated Circuit Market Drivers report. In 2011, LED-backlit TVs are expected to account for an estimated 37% of global TV shipments, up from 15% in 2010. IC Insights forecasts that LED TVs will represent 53% of digital TV shipments in 2012. [see LED TV, Smart TVs Drive Digital TV Units in 2011 as 3D TV Wanes]

Besides being thinner and lighter, LED-backlit TVs have rapidly gained favor among consumers because they tend to offer broader color range, improved contrast ratios, and use less power. Also, LED TVs are said to be more reliable, offering over 100,000 hours of life compared to traditional cold cathode fluorescent lamp (CCFL) LCD TVs, which are often rated at 20,000 hours. [Although I do wonder how they tested this — see "Lester the Lightbulb" discussions.]

In general, digital TV growth rates are expected to remain fairly flat in developed markets (e.g., North America, Europe, and Japan) through the forecast period, since the big upgrade cycle in these regions has mostly already occurred. However, India, China and other countries throughout the Asia-Pacific and Latin America are forecast to enjoy strong DTV growth. Fast-growth economies, increased disposable incomes, and large populations will drive this expansion. Asia-Pacific is undergoing a digital TV boom that some believe will result in 70% of homes having a DTV in 2015, up from approximately 35% in 2010.

That IC Insights report also notes how the method of delivering programming is quickly transforming broadcast television. Just as smartphones brought the Internet and thousands of applications to cellphone users, "smart TVs" are bringing Internet and Web 2.0 features to television sets and offering access to TV broadcasts, videos, movies, photos, and other content via the Web. An estimated 20% of television shipments in 2011 were smart TVs, but this is expected to increase to nearly 40% of in 2012. Consumers will be able to watch almost anything found on a Web site on their television.

While the leading edge of LED packaging is going wafer-level (see below) using bumping and backside TSV technology, the bulk of the packaging as it enters the backlighting market is still on lead frames as shown below for the Osram Golden Dragon. Package development for LEDs appears to be in its infancy similar to where bumped WLP devices were a decade ago. Expect to see rapid changes in LED packaging over the next five years.

For all the latest in 3D IC and advanced packaging, stay linked to IFTLE……….

IFTLE 74 The Micron Memory Cube consortium

Most of you by now have seen the announcement that Micron has joined with Samsung to create the "Hybrid Memory Cube (HMC) Consortium" with fellow founding members Altera, Open Silicon, and Xilinx. [link 1, link 2]

The consortium is built around Micron’s hybrid (previously referred to as "hyper") memory cube technology. The initial goal of the consortium is to define specifications for HMC. The HMC interface is totally different, having nothing in common with current DDR implementations, so it is felt that standardization and adoption by major producers and users is the only way that HMC will become a standard memory product for the industry.

We have previously addressed the fact that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can provide. The term "memory wall" has been used to describe the problem. A solution to the memory wall problem requires an architecture that can deliver increased density and bandwidth at significantly reduced power consumption.

Micron initially announced their memory breakthrough earlier this year [see IFTLE 38: "Of Memory Cubes and Ivy Bridges — More 3D and TSV"], and began releasing information at conferences this summer [see J.T. Pawlowski, "Hybrid Memory Cube: Breakthrough DRAM performance with a fundamentally re-architected DRAM subsystem", Proc. 23rd Hot Chips Symposium, 2011].

While DDR DRAMs have gotten bigger through the years by increasing the parallel arrays of DRAM cells on chip, they remain limited to the bandwidth supported by package I/O. DDR3-1333 and DDR3-1600 devices currently offer bandwidths of 10.66 Gbps and 12.8 Gbps respectfully. The HMC is a stack of multiple memory die sitting atop a logic controller chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. Both the number of contacts and their shorter lengths enable dramatically higher data transfer rates than today’s memory other memory architectures — Micron has shown prototypes rated at 128 Gbps.

Current DRAM burns a huge amount of the power in laptops and phones. Brian M. Shirley, VP of DRAM solutions at Micron, claims that the company’s hybrid memory cube technology "offers a 20-fold performance increase while reducing the size of the chip and consuming about one-tenth of the power," while occupying 10% of the volume of a DDR3 memory module.

[Performance & Power consumption Paradigm shift due to HMC (left); TSV stacked memory layers on logic layer (right). Source: Micron]

Micron reports that the HMC module achieves and exceeds 128 Gbps by using parallel channels. An image of the first-generation Micron HMC memory die showing the large number of I/O coming off each die:

[HMC Memory Device showing large Number of I/O. Source: Steve Liebson, Cadence EDA360 Insider blog]

Joe Jeddeloh, whose Micron team developed the logic portion of the HMC has described [link] the key "themes" of their technology as follows: "Instead of a DRAM die being one large device that has one set of I/Os on it, we break it into, say, 16 separate DRAMs, in essence much like a multicore processor. Each of those DRAMs has its own interface so when you go to access data, you go to a very local area of DRAM […]It’s a more directed access." Then, "we move that down the Z direction on a TSV."

When asked about the impact of 3D stacking on memory performance, Jeddeloh responded:

"When you think of a DIMM, maybe it has 4, 8, 16 [memory cell] banks in it, …once you go to a memory cube where you have these tiles and partitions, each of those has its own bank structure. So instead of 8 banks, you have 128 banks, 256 banks and each of these are put into parallel DRAM structures so you have a tremendous amount of concurrency available. You can think of a many-core processor coming at a many tiled memory system that marries up and can handle a lot of concurrent transactions."

In terms of mating this memory to today’s and future microprocessors, Jeddeloh commented that "As we go to more and more cores on processors [they become] more and more bandwidth-hungry. In this generation, you can’t stack the DRAM on top of the processor because the processor is too hot. That means the processor has to go off-chip to get that bandwidth [and] you need to connect a pipe to that processor that can bring in as much bandwidth at the lowest amount of power." Micron’s HMC technology, he explained, "can put more density in a very local area and put that right next to the processor." He also characterized power as the No. 1 theme going forward: "Once we reduce that power, we can create a smaller, more efficient I/O structure when the processor and the memory system are right next to each other. If you have, say, eight cubes hooked up to a processor, there’s a tremendous amount of bandwidth and concurrency that can happen in a very small area."

Concerning heat issues in the HMC, Jeddeloh noted that "DRAM doesn’t like heat; it messes up the refresh. If we are not on top of the processor, the heat is manageable. Once you create that low-power I/O […] and you’re not creating as much power within the cube itself, then you stack it up and pull the heat out the top."

[160 Gbps = 1 HMC or 15 DDR3-1333 DIMMS. Source: Micron Technology]

Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC), predicts that HMC impact will be seen in multiple markets such as high-performance computing, networking, video, medical, energy, wireless communications, transportation, security — basically any applications that will require the transfer of tremendous amounts of data. When asked about the Samsung partnership, he answered: "We need multiple sources for a broad adoption," since the industry is not comfortable with any sole source products. He indicated that the plan of record is to begin production in the second half of 2013.

At the recent Intel designer forum (IDF 2011) we found out that Micron teamed up with Intel to create the technology [link]. The company highlighted that a big impediment to scaling the performance of servers and data centers is the available bandwidth to memory:

"As the number of cores on a microprocessor increases, the need to feed the cores with more memory data expands proportionally. There [are] severe limitations to achieving high-speed and low-power using commodity DRAM […] We came to the conclusion that mating DRAM and a logic process based I/O buffer using 3D stacking could be the way to solve the dilemma. We found out that once we placed a multi-layer DRAM stack on top of a logic layer, we could solve another memory problem which limits the ability to efficiently transfer data from the DRAM memory cells to the corresponding I/O circuits."

Intel CTO Justin Rattner demonstrated the Hybrid Memory Cube toward the end of his keynote lecture which can be seen here [link]. Rattner noted that the HMC was "the world’s highest-bandwidth DRAM device with sustained transfer rates of 1 terabit per second (trillion bits per second). It is also the most energy efficient DRAM ever built."

It is currently unclear whether Intel holds any of this HMC IP — and it is equally unclear why Intel was not a founding member of the HMC consortium. IFTLE will follow this evolving story closely.

For all the latest in 3D IC and advanced packaging stay linked to IFTLE……….