Insights From Leading Edge

Monthly Archives: November 2017

ITLE 361 2017 IMAPS Part 1: Xilinx HMB Integration Challenges and More

By Dr. Phil Garrou, Contributing Editor

Let’s start looking at some of the key presentations at IMAPS 2017.


Gandhi of Xilinx gave an interesting presentation on “2.5D FPGA-HBM Integration Challenges.”

Heterogeneous integration of HBM (high bandwith memory stacks) with ASIC, GPU, CPU and FPGA is real and progressing quickly. Xilinx is the frst company to attempt HM integration with partitioned FPGAs in a 2.5D format.

Xilinx 1Xilinx recently announced HBM enabled 16nm Ultrascale FPGAs which are shown below. They are built using 3rd gen CoWoS technology jointly developed by Xilinx and TSMC. The claim is that these heterogeneously integrated packages are delivering 10X the bandwidth per HBM stack and 4X lower power than DDR-4 . These packages are 55 x 55mm2.


Interposer Design – µbump pitch on the memory stacks are set by JEDEC standards. There is no std for µbump pitch on FPGAs. For ease of interposer routing, pitches across the two die need to match so that an integer number of inter die signal lines can be routed in a uniform fashion between a pair of micro bumps. This is also required from a signal timing point of view.

Package Design and Process –

xilinx 2HBM-FPGA integration for the current 16nm product required changes to bump structure and lid type. The packages moved from eutectic solder bumps to copper pillar bumps with lead free solder and a change from a copper lid to a stainless steel stiffener ring was also required. This is shown in fig below. Precise control of bare die parallelism and flatness is required to enable heat sink attachment. In the shown figure, modeling shows that co-planarity is reduced by wider ring width and/or thicker stiffener ring. They were also required to change the BGA substrate to a lower CTE core to lower the co-planarity.

Challenges in bump assembly

Addition of the HBM stacks results in open area around the HBM stacks in the layout as seen in the above pic. This results in higher warpage. Bump size and underfill type must be optimized.

ETRI (Electronics and Telecom Research Institute) Korea

ETRI has examined the “Development and Stacking Process for 3D TSV Structures using Laser.”

As part of their 3D studies they have compared bonding results between using TC (thermocompression) and laser. The bonding procedure is shown below.


The max temp of the compression bonding was 240 °C for 200 sec at a force of 1 Newton. At a laser power of 200W the max temp reached was 260 °C at a process time of 10 sec.

They concluded that there was no difference in the solder joint morphology and the electrical resistances of bonded daisy chains for both assembly technologies was the same.


Kobus presented a “Alternative Deposition Solution for Cost Reduction of TSV Integration.” Use of TSV requires isolation, barrier and copper seed deposition into the etched vias. For low AR TSV one uses PECVD and PVD techniques for the depositions. For high AR vias ALD is sometimes required. PECVD offers the highest dep rate but poor conformality. ALD results in near 100% conformality irregardless of AR, but the thickness is limited and he dep time is very slow.

FAST (Fast Atomic Sequential Technology) combines CVD and ALD to reportedly rapidly give thick, conformal depositions.

Oxide liner dep from TEOS is compared below.

Kobus 1

Electrical properties of the deposition are reportedly enhanced with 150 °C deposition resulting in BV or 9MV/cm.

TiN barrier layer is from TDEAT (tetrakisdiethylamidotitanium) and copper seed from Cupraselect™. Copper seed dep comparing FAST with PVD are shown below. They report that the field thickness (on top), resulting from copper deposition to get 200nm of copper at the bottom of a 10:1 AR via, is reduced by 2X which effects the subsequent CMP time to remove it.

kobus 2

Claims of a 24% reduction on TSV processing cost are claimed.

For all the latest on Advanced Packaging, stay linked to IFTLE…


IFTLE 360 IMAPS 2017 – 50 Years and Counting

By Dr. Phil Garrou, Contributing Editor

IMAPS 50th

IMAPS (the Int Microelectronics Assembly and Packaging Society) 2017 was held this year near their Research Triangle Park headquarters, in Raleigh, NC, certainly a convenient location for IFTLE. Having started operations in 1967 as ISHM (Int Society for Hybrid Microelectronics), they changed their name and focus during my Presidential year of 1998 to IMAPS. This is the 50th year of existence for this nonprofit society. I emphasize the term nonprofit intentionally. This is important to me since the conferences we all attend request we give our free time to serve as presenters or session chairs or organizers and I want to be sure that the profits from such enterprises are going to a nonprofit and not into someone’s personal bank account, as is the case for so many of these conferences you and I attend. Basically, I don’t work for free unless it is a non profit, only seems right to me, so conferences that I give my limited time to, tend to be organized by IEEE and IMAPS.

My first IMAPS conference was in 1985 as my professional focus in Dow Chemical shifted from R&D on organometallic catalysts to the electronics industry. I was 35 but only a rookie in the electronics industry with lots to learn. This was the first electronics conference of my career (which I then followed up with the ECTC conference in the spring of 1986) and as importantly, it introduced me to many of the contacts and long term friends that I was able to develop in this industry through the years.

Fig 1

I recently took a look at the Proceedings (which I still have in my professional library) and during this trip down memory lane thought you might be interested in what was considered groundbreaking 32 years ago.

In the mid 1980s the industry was just getting comfortable with surface mount components and Harry Charles of Johns Hopkins was talking about “Design Optimization and Reliability Testing of Surface Mount Solder Joints”.

In the computer aided design session authors from Tektronix were sharing their thoughts on “Just-in-time Manufacturing – An essential technique for Process Control”.

In the Polymer Applications session, Englehard (that’s right Englehard the precious metals company) was showing us how to spin coat polyimide in their paper “Multi-layering with PI dielectric and metallo-organic conductors.” This paper had a significant influence on my personal career since, working for Dow Chemical at the time, I went back home wondering whether I could find a Dow polymer material that could be used for similar thin film polymer IC applications. This eventually led me to the discovery (it existed in the bowels of Dow R&D without a clear application need) and commercialization of BCB dielectric which by the mid 190s led to the commercialization of low cost bumping and WLP at FCT and Unitive and subsequently all the key bumping houses in Taiwan as they licensed the technology. By the early 2000s, BCB was being used in components put into nearly every cell phone being manufactured in the world!

The interconnect technologies session contained the paper “Recent advances in Die Attach Adhesives for Microelectronics” given by epoxy legend Dick Estes from Epoxy Tech. At the time polymeric die attach were not allowed in high rel military applications. He described the issues of thermal stability, outgassing and most importantly halide contamination of devices.

Kohji Nihei of Oki , later to become infamous as the photographer of the generation that proceeded me, gave the first paper I had ever seen describing the use of “LEDs for the electrographic, non impact printing of text and images” entitled “Development of High Quality LED Print Head” (shown below) Think that’s a technology with a commercial future?

Fig 2

For those of you that don’t remember Kohji, you should, both as a wonderful person and a technologist. Below he is shown a few years later in Japan with the American contingent at an IEEE VLSI workshop.

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

(l-r) Kohji Nihei (Oki), Len Schaper (AT&T, Alcoa, U. Arkansas), Garrou, Jan Vardaman (TechSearch), George Harman (NIST “Mr. Wirebonding”)

That’s enough of the past. Next week, we will begin our look at the 2017 IMAPS Conference content, I promise.

For all the latest on advanced packaging and nostalgia, stay linked to IFTLE…

IFTLE 359 ARM on IoT; SEMICON Taiwan Part 4

By Dr. Phil Garrou, Contributing Editor

Will IoT require “dirt cheap” packaging?

Those of you following IFTLE’s position on IoT know that while I certainly see a future where the wireless collection of data proliferates, I see this, in general, for extreme low cost packaging solutions, certainly not, as some have said in the past, an IoT using 2.5/3D solutions.

In seeming agreement with that conclusion, Rick Merritt of EE Times describing the recent ARMTechCon reports that the panel discussion on “Breakthrough Technologies enabling the future of IoT” concluded that the future of IOT could depend on a chip that sells for less than 50 cents, that SoCs will need new kinds of memories, connectivity and sensors to scale to dimensions the IoT will demand, and that the path to get there is still unclear. [link]

He reports that SRAM and flash memories, Bluetooth interfaces and sensors consume too much power to serve volume IoT nodes in 2027 where ideally, ARM reports, an end node SoC would consume just 10 microwatts/MHz and send and transmit data on a radio drawing only 1 or 2 mW. In terms of transmission, radios need to ultimately scale to power levels of a tenth the power of today’s Bluetooth Low Energy which perhaps will require a new radio maybe on new frequency bands which might take a 10-year effort to execute. Sensors will also need to explore new materials and design techniques to lower power, shrink size and add features. Sensors will need heterogeneous integration packaging technologies to integrate them into modules. “ … so the package becomes the sensor with silicon inside it”. Bottom line seems to be, as we have stated before, that the packaging solutions for IoT will have to be “dirt cheap”

SEMICON Taiwan continued…

Brewer Science

In his presentation on “New Materials for Fan-out WLP,” Tony Flaim of Brewer proposed an interesting new fan out concept where cavities are laser drilled into a laminated sheet, chips are inserted face up into the cavities and thin film RDL is created over the chips as shown below.

Brewer 1



IFTLE is not a big fan of making technology decisions based on cost modeling. My past experience has shown that he cost models that I have used are generally very accurate when all the inputs are well known and not very accurate when the inputs are being “guestimated”. Having said that, I do like the slide presented by Chet Palesko of SavanSys Solutions on the general comparison of embedded die vs FOWLP vs TSV solutions shown below…

Savansys 1


ITRI always gives us a nice update on activities in Taiwan. Below we see that Taiwan foundry services currently account for 70% of the world wide market and the Taiwanese IC packaging and test services account for 55% of the world wide SATS market.


Global Foundries

Dave McCann of GF showed a nice process flow for their 2.5D production where the interposer fab, logic fab, memory fab and OSATS must work together to deliver the finished product.


Next week, we will begin our look at IMAPS 2017. For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 358 SEMICON Taiwan Part 3: ASE & Powertech Fan Out Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at 2017 SEMICON Taiwan.


John Hunt of ASE discussed his thoughts on “Fan Out Packaging – Simple to Complex”.

An interesting slide was his chronology of wafer Level (WL) packaging sine the adoption of bumping and RDL (the advent of Taiwan licensing the FCT technologies).

ASE 1-2

Hunt divides fan out (FO) categories into low density and high density options:

  • Low Density fan out

– Less than 500-600 I/O

– L/S > 8µm

  • High Density fan out

– Greater than 500-600 I/O

– L/S < 8µm

Early applications for low density FO include baseband and Rf transceivers. New opportunities include:


Early high density fan out opportunities include PoP and SiP

New Opportunities include:

– APU + memory

– GPU + memory

– Network applications

– SiP/Modules

Note the GPU and Network apps begin to intrude into the space carved out by Silicon 2.5D. Such a product is described below:


Hunt showed the following ASE fan out package platform:



David Fang, CTO of Powertech discussed PTI panel level processing developments.

– Packaging for more than Moore modules is usually larger than 10x10mm and thus panel level processing provides 3-5X the efficiency of wafer level even at 300mm.

– They have found that the initial investment per module is 30-40% higher for panel level fan out modules than for fan in WLP.

Continuing challenges for panel processing include:

– No worldwide standards

– Tool and accessory readiness

– Process difficulties, i.e. panel warpage, chip shift, fine line patterning

An interesting slide details their thoughts on panel equipment selection based on technology from the Wafer, LCD and PWB industries.

powertech 1

Powertech fan out solutions are shown below.

powertech 2

For all the latest on Advanced packaging, stay linked to IFTLE…