Insights From Leading Edge

Monthly Archives: December 2010

IFTLE 29 IEEE 3D IC Test Workshop Part 2

Continuing with our discussions on presentations made at the 1st IEEE 3D IC Workshop in Austin.

NC State – TSV Test prior to stack

During wafer test, it is valuable to be able to determine which TSVs are likely to yield when used, and which are not. To detect failure in TSVs, an electrical test needs to be performed before 3D integration and chip packaging. Paul Franzon and co-workers at NC State propose three methods to test Through-Silicon-Vias (TSV) electrically prior to 3D integration: (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests detect one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate 1 bit pass/fail signal. All these methods can be implemented for test-before-stacking, to attempt to increase assembled yield.

The sense amplification and the capacitive bridge test structures can estimate the TSV capacitance to test void defects. The capacitive bridge circuit is more sensitive but consumes more area than the sense amplifier sensor. The sense amplification method cannot detect voids isolating less than approximately ±10% of the TSV. The potential test escape rate is proportional to what percentage of TSVs that have voids isolating 10% of the TSV capacitance or less. The leakage current test circuit can measure the resistance of dielectric layer to test leakage defects with much more sensitivity than the sense amplifier method. All the simulation results above show that the parameters of TSVs can be tested by simple circuits and the measurement data can be streamed out serially by a scan chain.

TSMC – Electrical Tests for 3D IC with TSV

Chen and co-workers at TSMC have identified five main categories of “faults” (i.e. performance failure modes) in 3DIC TSV with microbumps:
1. Faults due to miss-alignment
2. Faults in the Cu pillar
3. Faults due to impurities
4. Faults due to substrate
5. Faults in the microbump

In terms of alignment, they report two possible failure issues. The type 1 failure is due to an alignment shift which results in smaller overlap area contact and thus higher resistance. The type 2 failure occurs when there is severe miss alignment and a complete open occurs.

The second category is related to the Cu TSV. Type 3 failures come from voids in the Cu TSV which may be caused by electromigration. The resistance in the TSV becomes larger and the RC delay increases. Type 4 failure occurs due to breakage in the TSV by improper handling or other procesing issues and will result in an open circuit. The type 5 failure is due to failure to completely fill the TSV. This will also increase delay due to the higher resistance.

The third failure mode is due to impurities during processing. Type 6 failure is due to impurities between the TSV and the microbump which increase the contact resistenace and thus the signal delay time. Type 7 failure is due to impurities between the microbumps which also increases the contact resistance and thus the signal delay.

The fourth and fifth failure modes deal with failures in the substrate and failures in the microbump. Type 8 failure is due to non uniformity in the insulation liner which can result in a leakage path from the TSV to the substrate. Type 9 failure results in an open circuit from Cu TSV delamination from the substrate due to the thermal stress of the process. Type 10 failure is due to deformation of the microbumps or the wafer warping and the separation of the two microbumps causing discontinuity. Type 11 failure is due to shorts between the two microbumps.

The Table below compiles failure modes vs required testing which includes continuity, resistance, capacitance, leakage and high frequency performance

Test structures are integrated into the 3D IC test flow as shown below:
TSMC reports that besides testing, thermal issues, electromigration, stress sensor, redundancy and ESD are still waiting to be solved.


In a presentation covering DFT (design for test) Qualcomms Michael Laisne concludes that there are two primary defect classes: a) interconnect related defects and b) stress related defects. Either of which could manifest itself as a “stuck-at” or speed-related failure. He lists the main causes of interconnect-related defects as:

– substrate to TSV shorts,
– parasitic capacitance or resistance between the substrate and TSV causing speed-related failure,
– capacitive coupling between adjacent TSV causing both static and at-speed failures
– microbump opens and shorts, especially due to excessive warpage (opens) and misalignment (shorts)
– shorts due to interactions with TSV’s
– shorts and opens in the RDL

ST Ericsson

Stephane Lecomte of ST Ericsson reports that the first 3D TSV application they foresee in cell phones is wide IO memory which is currently undergoing JEDEC standardization. We have recently reported on similar conclusions from Nokia [see IFTLE 19,”Semicon Taiwan 3D Forum Part 2” ]

Most of the manufacturing issues, they feel are still tied up in the business model / infrastructure / supply chain issues that have yet to be resolved. They feel that boundary scan testing will be defined within JEDEC, but that BIST remains very manufacturer dependent.


ARM presented an interesting slide depicting the Mb/sec requirements for several common devices (shown below)

Certainly we would all agree that 3D IC test has come a long way over the last few years. All of the major design and test companies are now focused on integrating products so that full 3D IC integration can become a reality in the near future. For those worried that 3D still looks like it is many years away, I refer you back to the Qualcomm presentations that indicate that first generation products do not appear to have significant roadblocks in either thermal, design or test. It is for the future generation partially or fully reconfigured structures that major changes in design and test will be needed [ see IFTLE 9, “3D in and Around the Moscone

Lastlyâ??¦..One of the IEEE 3D Test Conference chairs requested that IFTLE model their midnight black knit shirt, so below we find our “mature” model showing off his shirt while reading the New York Times # 1 non fiction best seller “Handbook of 3D Integration” by Garrou, Bower and Ramm, available at !

â??¦â??¦..Merry Christmas and Happy Holiday season to all our IFTLE Readersâ??¦â??¦..

For all the latest in 3D IC and advanced packaging in 2011 and beyond, stay linked to IFTLEâ??¦â??¦..

IFTLE 28 Testing 3D ICs Deep in the Heart of Texas

We have been discussing test as a significant issue for the commercialization of 3D IC technology for a few years now [see for example PFTLE 108 ”3DIC Test”, PFTLE 102 “The Four Horseman of 3-D IC Integration”, PFTLE 100, “3D IC in the City by the Bay“,IFTLE 13 “3D In and Around the Moscone part 3” , IFTLE 5, “2010 DATE in Dresden

The IEEE Int Test Conference (ITC) held in Austin in November had a full-day tutorial, several technical papers, and a panel session, all on 3D-TEST. This was followed by a dedicated 3D-TEST Workshop, the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits “3D-TEST” which was chaired by Yervent Zorian of Virage Logic and Erik Jan Marinissen of IMEC. No one can any longer say that the industry is not focused on addressing 3D test.


The technical program consisted of: an Opening Keynote by Bob Patti of Tezzaron); an Invited Address by Brion Keller of Cadence; invited talks by Synopsys, ARM, IMEC, Qualcomm, Avago Technologies, ST-Ericsson, and Texas Instruments and technical papers from Cascade Microtech, Virginia Tech, Fraunhofer, TU Delft, NCSU, Mentor Graphics and, TSMC. The conference had financial support from  Advantest, ARM, Intellitech, Mentor Graphics, Scanimetrics, Synopsys, SynTest, Tezzaron , and Tokyo Electron.
IEEE Computer Society 3D Test Standardization Group
Marinissen presented the early results of the IEEE Computer Societies TTSC Standardization study group on 3D Test. Most of the major players are participating
The following standardization needs have been identified:
Bob Patti once again reiterated that the killer application for 3D IC will be what he calls “split die”, i.e. removing embedded memory from SoC and bonding it directly to the logic chip as shown below.
Tezzarons form of BIST is called Bi-STARâ??¢ by Patti, who claims that it “..tests and compares 2304 bits/clock cycle; more than 100 times faster than can be achieved by any external memory tester” Reportedly Bi-STAR can test and repair:
• Bad memory cells
•Bad line drivers
•Bad sense amps
•Shorted word lines
•Shorted bitlines
•Leaky bits
•Bad secondary bus drivers
Sanjiv Taneja of Cadence lists the following as Design and Test Challenges
• Front-end design
– Logic synthesis with 3-D partitioning
– Logic synthesis with 3-D physical awareness
– 3-D design/timing/power constraints
– Equivalence checking across multi-chip RTL/netlist
• Physical design and analysis
– 3-D floorplanning and partitioning
– Thermal/TSV-driven placement
– Global and detailed routing with TSV
– Parasitic extraction with 3-D electrical modeling
– IR drop and thermal analysis with TSV, Silicon interposer
• Chip-package co-design
– 3-D connectivity checks and constraint management
·  Test Challenges
– New defect types (defects due to thinning, TSVs)
– TSV Interconnect defects
– Limited test access with challenges similar to SiP
– Redundancy and repair of TSVs
– Key Technical Requirements
• Ultra-low pin count compression
• Reduced Pin Count Test
• Pattern Fault model
• 1149.1/1500 support
• Creation of KGD after wafer test
• A means to test the TSV interconnect between stacked die
• A means to test inside the die of the stack
Cadence points to the integration of design and test as the only way to solve these complex issues and that concurrent optimization for area, timing, power and testability is the only means to achieve required predictability.

Cascade Microtech – Probing of TSV at 40 um pitch
Ken Smith of Cascade Microtech indicates that contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards can achieve.
Smith claims that there is no known physical roadblock to scaling basic card mechanics to much smaller dimensions. To reduce the probe pitch by a factor of k, the basic scaling required is to reduce all of the probe’s dimensions by k, along with maintaining constant pressure at the probe tip.
Cascade claims their high-density MEMS probe card technology make 1 gram tip forces feasible and very low pad damage possible at 40 micron array pitch.

In order to minimize pad damage, it is desirable to probe at the lowest force range that yields stable contact resistance. Contact resistance is a function of probe tip size, shape and metallurgy; probing force (pressure); substrate metallurgy; test current level; and contact cleanliness (determined by the cleanliness of the probe tip, DUT surface, test environment as well as the cleaning regimen).
Smith claims that “..the measured results to date indicate successful scaling of mechanical probing to array pitches of around 40 um. Practical probe cards are capable of 40 um pitch and tip forces below 1 gm. These lithographically fabricated probe cards enable  scalability to lower cost  just as IC linewidth scaling has reduced the cost of IC functions. Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe is roughly proportional to the probe area”
Smith reports that pad damage at these low forces is extremely small with scrub marks less than 100 nm deep.
We will continue our discussions on the 3D Test Workshop in the next blog including an exclusive photo of the IEEE 3D Test with a surprise model !
For all the latest on 3D IC Integration and Advanced Packaging stay linked to IFTLEâ??¦..

IFTLE 27 Era of 3D IC Has Arrived with Samsung Commercial Announcement

Back in Nov 2008 PFTLE called on Mick Jagger and “Mr Jimmy” to explain why we “don’t always get what we want". What we wanted two years ago were commercial announcements, from someone, from anyone using 3D IC technology. [ see PFTLE 53, “You Can’t always Get what You Want”] While there were no blockbuster announcements that week in the fall of 2008 we did get assurances that the industry was steadily, if not rapidly, moving forward and that we are not wasting our time or money chasing this technology (or at least we hoped so).

Well, we often hear that “all things come to those who wait” and indeed this past week for those of us who are 3D prognosticators, our dreams have come true. Not that there was any reason to doubt after the Elpida,UMC, Powertech partnership announcements of this past summer, but I’m sure lots of 3D enthusiasts broke out the champagne this week after the announcement by Samsung. Both the Elpida and Samsung announcements contain all (3) requirements for full 3DIC; i.e thinning, stacking and TSV.

Similarly, this weeks IBM announcement following the Xilinx /TSMC/Amkor announcement a few weeks ago [ see IFTLE 23, “ Xilinx 28 nm Multidie FPGAâ??¦” ] gives added credibility to the commercial viability of high density interposers with TSV for advanced packaging solutions. With multiple announcements in each category now “under our belts” IFTLE proudly announces that the Era of 3DIC has arrived.

As was the case with image sensors [ see PFTLE 46, “…..on Mechanical Bulls, Rollercoasters and CIS with TSV” ] we can expect other memory producers to follow with announcements or eventually loose market share. Will Hynix or Micron announce next ?

Samsung Memory Stack

On Dec 7th Samsung announced that it “â??¦has begun mass production of 8GB DDR3 memory modules based on the SODIMM form-factor used by many notebooks and mobile workstations”. The modules are based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology. A single 8GB DDR3 module using the new technology is claimed to offer a 53% power savings compared to two 4GB DDR3 modules, and a 67 percent power savings compared to 1.8V DDR2 components. Samsung announced plans to apply the higher performance and lower power features of this TSV technology to 30nm-class and finer process nodes. This is only a two chip stack, but it is the beginning.
The modules are purposed for use in high performance servers where its TSV technology is a key to lower power consumption while increasing memory capacity and improving performance. Adoption is expected starting in 2012. The modules will be available as an option in Dell’s Precision M6500 mobile workstation, which will fill four slots totaling 32GB of memory. There was no indication of pricing or price comparison to non 3D components.

IBM 3D Interposer

The following day, IBM and Semtech announced that Semtech will use IBMs 3D TSV technology to develop a high-performance ADC/DSP platform for “â??¦ fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems”.

Calling the technology a “â??¦ first-generation 3D multi-chip module” Semtech will utilize IBM’s 300 mm 3D interposer technology to interconnect ADC functions in IBM custom logic (SOI-based Cu-45HP technology) with interleaver ICs (IBM’s 8HP BiCMOS SiGe technology). The disparate technologies are connected through a single 90 nm wiring layer on a 3D interposer, which supports a bandwidth of greater than 1.3 Tbps in this design.

Ultra high density capacitance is provided by integrating deep-trench (DT) capacitors at the top surface of the interposer. The interposer connects to the next level package with copper TSV technology. The figure below shows SEM cross sections of the interposer chip and deep trench capacitors.

IBM will provide semiconductor fabrication, wafer finishing and assembly for Semtech. Integration of data converters with DSPs reportedly has been a difficult problem due to mixed IC technology requirements and lack of high power, high bandwidth interconnect. The 3D technology allows integration of the CMOS and SiGe technology at very high bandwidth and with low power to provide a high-performance module solution.

Semtech will have first ADC/DSP prototype modules available in 2011. Near-term applications include 100 Gbps coherent receiver for fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems.

GSA Creates 3D Integrated Circuit (IC) Initiative

The GSA (Global Semiconductor Alliance ) has announced a new 3D IC Initiative. The GSA’s goal is to help accelerate an industry-wide transition to make 3D IC technically feasable, as well as cost-effective, for a wide range of applications and increase ROI for early adopters.

Part of the 3D IC initiative includes the formation of the 3D IC Working Group which will include participants from the major semiconductor companies, the supply chain including EDA, packaging and foundry. The GSA hopes to continue to work with other interested organizations on standards and other synergies to drive economies of scale and therefore has initiated relationships with IMEC, ITRI, SEMI , SEMATECH and Si2 to help in such efforts.

The GSA will hosts its second annual Memory Conference on March 31, 2011 in San Jose. The theme for the 2011 conference will be Memory and Logic Integration and the Benefits of 3D IC Technology.

SEMATECH /SIA /SRC Initiate 3D Enablement Program

SEMATECH, the SIA (Semiconductor Industry Association) and the SRC (Semiconductor Research Corporation) have established a “3D enablement program” to drive industry standardization efforts and technical specifications for 3D heterogeneous integration.

The new 3D program, launched by a group of existing member companies in SIA and SEMATECH, will focus primarily on developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. To achieve this, SEMATECH will partner with SRC to enable select university research projects. The program will address these industry infrastructure gaps in phases. First efforts will focus on developing the necessary standards and technical specifications, followed by planning activities to identify the key areas for developing design tools to support 3D chip design.

The 3D Enablement program is open to international fabless, fab-lite and IDM companies, outsourced assembly and test (OSAT) suppliers, and tool vendors.

Coming up next;

â??¦..IEEE 3D Test Workshop
.â??¦.IEEE 3DIC Conference
â??¦..RTI 3D-ASIP

For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦.

IFTLE 26 Adv Pkging at the 2010 ESTC

The ESTC (Electronic System integration Technology Conference) was set up to be the European equivalent to the sister ECTC (USA) and EPTC (Asia) conferences. This years conference in Berlin attracted ~ 480 attendees who saw 160 presentations, 4 poster sessions, a 3-day industry exhibition, workshops and short courses.

Rolf Aschenbrenner (right) , President of IEEE CPMT overlooks ESTC in Berlin


We have previously discussed the significant inroads being made by Cu WB (wire bonding) [ see PFTLE 86 “Advanced Packaging from Rimini”, 07/12/2009 ]. At the ESTC ASE’s Bernd Appelt gave a update on the status of Cu WB in ASE.

Cu WB has been around for some 20 years but up till now has been limited to high power applications with wire diameters over 2 mil. Now that commodity gold prices have surpassed $1000 / oz there is significant demand to drive down the cost of gold WB. Fine diameter Cu wire refers to wire diameters below 1.2 mils, normally 0.8 mil, either Cu wire or Pd coated Cu wire (Nippon Steel).

Gold is very resistant to oxidation and corrosion. . While copper has electrical, thermal and mechanical advantages it also presents challenges due to the mechanical properties as well as its propensity for oxidation and corrosion. To overcome Cu oxidation during electronic flame off (EFO) that leads to a free air ball (FAB) of an undesired appearance, forming gas ( 95% N2, 5% H2) is widely used. Spherical ball shape is a good indicator that an ‘oxide free’ ball has been formed.

According to KNS, the cost of Pd-coated wire is currently about twice that of bare copper wire, but still offers savings over gold wire. The palladium coating greatly reduces oxidation on the surface of the wire. allowing a nitrogen gas atmosphere (no H2) during ball formation. The oxide-free surface of Pd-coated wire also results in a more robust stitch bond with higher stitch bond pull strengths and the shelf life of the Pd-coated wire is longer than bare copper wire.

Al splash, which can be quite pronounced, must be contained within the bond pad opening (BPO) as shown in the Fig. below. Residual Al thickness should be 100 nm minimum. This thickness typically survives JEDEC temp cycling of more than 1000 hrs.

The wire pull and ball shear strength at time zero are considerable higher than for corresponding Au wires although the AlCu intermetallic compounds is very thin.

The mold process and pre-mold plasmas do not require any change other than the usual optimizations of plasma. Concerns have been raised about the reliability of standard mold compounds as do to the propensity of oxidation and corrosion of Cu.

ASE reports that reliability has been demonstrated to exceed 2x standard JEDEC testing and is continuing. More than 400 million devices have been shipped by ASE from six different factories. More than 1,500 wire bonders are running with Cu wire and they expected that by the end of 2010 this number will increase to 3,000.

KNS – Thin Die Pick and Place

Common attributes to all thin die processes include: 1) relatively long pick times (typically 300 to 600 msec) to avoid cracking of the dice and 2) relatively long place times (500 msec up to 2 sec) in order to guarantee good die attach quality. Peeling the die from the wafer mounting tape typically requires a large vacuum suction force which can be achieved by a large number of large diameter vacuum holes. On the place tool, however, the large vacuum holes need to be avoided in order to minimize the die deformation during the place process, since this can lead to undesired air inclusions (voids) between the die and the substrate or the underlying device. KNS describes their parallel pick and place architecture (shown below) which they claim both units per hour and die attach quality. With the parallel pick and place architecture the pick process of the subsequent die can already be initiated during the place process of the first die.

ST Micro/ ST-Ericsson / Leti – WB vs 3D IC

ST Micro, ST-Ericsson and CEA Leti showed results of their study comparing a wireless video product built and compared in WB vs TSV constructions.

Chips were fabricated using a 65nm node CMOS process including seven Cu metal layers with low-k. TSV were 60μm diameters on 120μm pitch in 120μm thick wafers. Cu pillars used for die to substrate connection were 70μm diameter on 130μm pitch and 80μm height. The BGA package (4x4mm) included 65 balls on 0.4mm pitch.

In their test case, no significant performance differences were seen between both versions of the product. ESD, considered a crucial topic for 3D integration was examined. They noticed no major difference between the two versions of the products, concluding the TSV version of the product did not exhibit a more critical ESD behavior. They conclude “there’s no important show-stopper with the technological bricks that are currently available for TSV integration today”

On Semi – Low Profile WLP

To meet requirements for thin smart phone products, ON Semiconductor has developed “LPCSP” a low profile CSP (WLP) with a 0.275 mm thickness.

While it is well known that increased solder ball height increased reliability, the goal of 0.275 mm thickness could only be achieved by reducing the ball height and/or the silicon wafer thickness. A silicon thickness of 200 um was chosen due to automated handling equipment limitations. The LP-CSP technology does not require special assembly handling, additional assembly steps or underfill. It is clear from the data that both silicon thickness and bump height reduction were necessary to ensure board level reliability performance of the LP-CSP is comparable to WLCSP.

IMEC / Amkor – Reliabilty of Cu-Sn IMC Microbumps in 3D Stacking

IMEC and Amkor have studied thermal cycling and electromigration, on fully packaged Si-to-Si stacks bonded with Cu-Sn intermetallic (IMC) micro-bumps.

While the presence of small voids at the interface between Cu and Cu3Sn becomes more pronounced with continued ageing, during thermal cycling, these voids do not affect the daisy chain resistance during temp cycling between -40 and +125 C. The Cu-Sn IMC bumps survive thermal cycling for more than 3900 cycles.

Resistance to electromigration appears strongly dependent on Sn thickness showing an improved performance for thinner (3.5 µm) vs thicker (8 µm) Sn. For 8 μm Sn bumps, almost all available Cu is fully consumed (5μm on each side of the joint) and the Cu3Sn phase reaches the Cu damascene layers. Voiding inside these thin layers is reportedly detrimental to the interconnection stability. A more conservative ratio of Cu and Sn is therefore suggested.

While IMC bumps outperform standard solder flip chip bumps, the authors recommend that an overall reduction of the void formation may be advisable for further reliability improvement.

They conclude that appropriate packaging of these Cu-Sn IMC bonded Si-stacks results in overall excellent thermo-mechanical and thermal-electrical behavior for various reliability test conditions which makes them highly suitable for connecting fine pitch advanced substrates.

Amkor – Wafer Level Fan Out

When it comes to fan out WLP Amkor has appeared behind Infineon partners STATSChipPAC and ASE. Amkor presented wafer level fan out technology developments using Ajinomoto build-up film (ABF), laser ablation via generation processes and buried pattern PCBs, which they claim results in low cost and high electrical performance.

In the first process ABF is laminated to the reconstructed compression molded wafer, micro-vias are formed by laser drilling and Cu RDL interconnect is plated and pattern defined.

A second process based on a buried-pattern PCB substrate was also described for fabrication of FO WLP. By using buried-pattern PCB, similar to what is used for high density BGAs, laser ablation of the vias is not necessary. The buried-pattern substrate is delivered from PCB manufacturer with open (non filled) through vias which are seeded and plated from the backside after front side chip attach. After polishing, RDL and ball placement the devices are singulated.

Fraunhoffer IZM – Thin Stackable Embedded Chip Packages

In two separate presentations researchers from Fraunhoffer IZM and coauthors detailed now methods to construct thin stackable packages.

Under the framework of the EU-funded project “HIDING DIES” program industry and research organizations worked with Fraunhofer IZM to develop embedding technology based on embedding thin chips into build-up PCB materials. Electrical contacts to the chips are realized by laser-drilled and metalized microvias. A follow up EU-funded project “HERMES” has the broader scope of furthering the embedding technology and bringing embedding technology into production with the goal of embedding components in 18 x 24 inch PCBs.

Dies can be either placed face-down on the substrates or face-up. The Fraunhofer IZM technology focuses on the face up approach in combination with the formation of laser micro vias. The process flow is shown below using resin coated copper (RCC) to embed the die:

A QFN package results when the chip is attached to a metal substrate as shown below. Both top and bottom contacts are directly accessible for better heat dissipation which is of importance for devices like power chips.

Such structures can also be stacked into 3D PoP configurations.

Infineon – eWLB

Infineon presented the latest developments in connection strategies for 3D-eWLB and the challenges of the technology this development.

Multichip- eWLB – a minimum distance between two dies is set, depending on amongst other things the size of the filler particles. Typically the minimal fillable gap is 2.5 times the maximum filler size, but this is also depending on the thickness of the silicon die(s). They report excellent mold compound filling behavior of 250 μm die to die gap. After the pick and place process step, no special multi-die specific process step are reportedly needed. The wafer is molded with standard mold compound and the same dielectrics and redistribution lines are applied as for the single die eWLB. Die shift and wafer warpage after molding was found to be equal to single die eWLB. Reliability testing including Temp cycling and BLR drop testing showed no difference between eWLB and multichip eWLB.

Stacked eWLB (or ePoP) – the technical advantages of eWLB PoP stacking are reported to be :
– Low profile and small lateral dimensions
– No interposer requirement (reduced number of interconnects, reduced cost)
– Use of top packages with standardized ball array

Connection in z-direction for a “ePoP” package can reportedly be realized in two ways.
– drill via holes by laser
– via bars, produced in PCB technology, can be molded into the reconstituted wafer

The process flow for the latter is shown below. The chips and the PCB based bars are placed on the mold carrier and the reconstituted wafer is generated via compression molding. After reconstitution the artificial wafer is ground down to make the via bar accessible for the connection with a redistribution layer. It consists of a dielectric on bottom side, redistribution layer and solder stop on top and bottom side.

Hope to see many of you at next weeks RTI 3D-ASIP conference in Burlingame CA (link)

For all the latest on 3D IC Integration and Advanced Packaging stay linked to Insights From the Leading Edge, IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦