Author Archives: sdavis

IFTLE 315: IMEC Leads at IEEE 3DIC 2016

By Dr. Phil Garrou, Contributing Editor

The 7th annual IEEE 3DIC Conference took place in SF a few weeks ago chaired by Paul Franzon of NC State and Bob Patti of Tezzaron. Without question, IMEC led all participants with several key papers at the conference. This week, IFTLE will look at IMEC contributions.

In their paper “Continuity and Reliability Assessment of a scalable 3 x 50μm and 2 x 40μm via-middle TSV Modules” IMEC describes a scalable via-middle module process, featuring an ALD oxide liner, a thermal ALD WN barrier and an electroless NiB platable seed. The module has been downscaled from 3μm to 2μm diameter TSVs. Both the front side to back side TSV continuity as well as the TSV reliability were found to be satisfactory.

When increasing the aspect ratio of the TSV from 10:1 to 17:1 and even 20:1 (for 3 x 50μm and 2 x 40μm respectively), the use of a conventional PVD barrier and seed reaches its conformality limits, as very thick layers need to be deposited in order to assure a continuous film at the bottom of the TSV. For this reason, an advanced and scalable 3 x 50μm TSV metallization scheme was developed and further scaled down to 2 x 40μm diameter/depth TSVs.

IMEC vias middle process flow is shown below.



The oxide liner is deposited in an ALD oxide system . 100% conformality is obtained over the entire TSV depth for 2 x 40μm TSV structures. The 17nm thermal ALD WN barrier is deposited followed by a 100nm electroless NiB seed . Both layers exhibit highly conformal deposition. The TSV copper electrofill is done on an ECD system. Void free filling is obtained for these 2 x 40μm TSVs placed at pitch of 5μm.

The device wafers are temporary bonded to a Si carrier wafer, using Brewer Science Zonebond process. Device wafer thinning is done by mechanical grinding, rough followed by fine grinding, to provide polished surfaces. The mechanical grinding is stopped before the first Cu TSVs are reached, thus leaving a silicon layer between the wafer backside and the tip of the TSVs. A wet process based on HF/HNO3 isotropically etches a few microns of Si, followed by an additional wet TMAH step, selective to the liner oxide, to reveal the TSV bottoms. Cu of the TSV remains encapsulated in the oxide liner. The back side passivation layer is processed on the revealed via bottoms. A low temperature nitride layer is deposited on the wafer backside, and a thick resist layer planarizes the whole surface. Blanket etch back of the layer without photolithography, to expose all TSVs while a thin resist layer remains on the field. The passivation layer together with the oxide liner are etched away in a dry etch process selective to the barrier metal. Finally, the resist is stripped.

Then back side RDL is integrated with a semi-additive process. TiW/Copper barrier and seed deposition, is followed by copper plating.

The liner/barrier integrity is verified by using the controlled I-V method The TSVs are tested in both copper confined (accumulation) and copper-driven (depletion) mode to check the quality of the oxide liner and WN barrier combination. The IVCTRL test indicates excellent barrier/liner reliability of the 2 x 40μm TSV.

In the IMEC paper “Die to wafer 3D stacking for below 10um pitch micro-bumps” reports on the process flow for embedded bumps for below 10um pitch micro-bumps. A process is introduced to fabricate Sn micro-bumps with zero undercut . Revealing bumps and planarization was done by CMP and surface planer. Initial TCB stacking showed well aligned bumps for 5um pitch daisy chains, good mechanical strength of bonded chips and IMC formation between Sn and bottom Cu pads. Calculations show that replacing Cu with Co and Ni will result in less material consumption which is interesting for sub 10um pitch micro-bumps.

In their embedded micro-bumps approach, micro-bumps are embedded in either organic or inorganic dielectric materials. As shown below UBM is processed in a damascene type approach and solder is embedded in a non-cured polymer or WLUF (wafer level underfill). Since a damascene process is used for UBM, spacing between them can be reduced. For 5um pitch, 1um spacing is used. Selection of solder diameter is based on alignment capability of TCB tool.

imec 2

It was found that at temperatures below 120oC, Cu/Sn IMC grows faster than Co/Sn or Ni/Sn IMC while at higher temperatures close to melting temperature of Sn (233oC) Co/Sn and Ni/Sn will grow faster.

The figure below shows plated Sn micro-bumps in 5um pitch and 40um pitch regions before seed etch.

imec 3


For die to wafer stacking an advanced high precision thermocompression bonding tool from Besi with alignment accuracy close to 1um was used. Total profile is around 10s with interface temperature of 250oC and force around 10-15kg. In order to prevent Cu or Co pads from oxidation during bonding, passivation layers such as SAM, NiB and immersion Au were used.

In their paper “Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects” IMEC reports that by taking into account the described alignment tolerances, via last diameters of 1μm enable 2μm pitch TSV interconnection densities.

When looking at dielectric bonding with via last TSV connections. Two wafers are finished with a very smooth, low-topography dielectric layer. The wafers are cleaned and the surfaces are activated by plasma processes. The wafers are subsequently aligned with high precision and brought into contact, resulting in a spontaneous room temperature wafer-to-wafer bonding. After annealing the bond between the wafers becomes permanent. The top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and bottom wafer. The integration scheme is shown below.


The structure has 1μm diameter TSV on a 2 μm pitch. On top of the FEOL stack, 300mm top and bottom wafers have 1 damascene metal layer, called MET1T in the top wafer and MET1B in the landing or bottom wafer. Both wafers are finalized with a planarized SiO2 and a SiCN bonding layer. A SiCN bonding layer is preferred over SiO2 or SiON for its higher bonding strength. The top wafer is aligned to the bottom wafer and bonded at low temperature with high accuracy to the bottom wafer.

The bonding processing is completed by the post-bonding annealing process of 2 hours at 350°C to strengthen the bonded dielectric interface. After aligned bonding of the wafers, the top wafer is thinned to 5μm Si. The thinning process is a combination of wafer grinding, Si CMP and Si dry etch.

The wafer-to-wafer interconnects are realized with 1μm diameter TSVs, defined by through-5μm Si alignment on a high accuracy scanner. The smoothness of the Si surface is critical to enable the alignment. The TSVs are aligned to the corresponding landing pad.

In their final paper IMEC discusses “High-Density and Low-Leakage Novel Embedded 3D MIM capacitor on Si Interposer”. In this work they present a technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high as 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having a breakdown voltage of 10.5 V and > 10 years lifetime (T50%@1V,100 °C = 5.18e16 s).

The process flow is shown below.

imec 5

The list of investigated 3D MIM capacitor is shown in Table below.

imec 6


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 314 IMAPS 2016 part 3: Shinko’s iTHOP; Yole Predicts Sharp Rise in FOWLP Mkt

By Dr. Phil Garrou, Contributing Editor

Finishing our look at the 2016 IMAPS Conference, let’s take a look at presentations by Shinko, Yole, UCLA, Maxim and Asahi Glass.


Kyozuka of Shinko Electric discussed their i-THOP (integrated thin film high density organic package) package for mobile applications. Based on the trend of partitioning large chips into smaller functional units that are the connected on a high density SiP, Shinko sought to develop a high density (2/2 L/S) organic package for use in mobile devices. It involves the integration of thin film layers on a conventional build up PCB as shown below. Design specs and process flow are shown below.

Shinko 1


A discussion of the “embedding resin” which was not identified indicated that materials “B” and “C” “…can be applied for this structure” since no cracks were seen after T/C testing. IFTLE worries about these choices since these materials reportedly exhibit tensile strength between 60 & 100 MPa and elongations of < 2.5%.


Azemar of Yole discussed FOWLP market and technology trends. Yole sees the fan out market splitting in the future into (1) single die applications such as baseband, power management, Rf transceivers etc and a (2) high density market exemplified by the TSMC “InFO” that include larger IO count applications such as processors. This explains the sharp jump in their market forecasts as shown below.

Yole 1


Subu Iyer and his group at UCLA have been taking a look at Cu-Cu thermo- compression bonding for die to substrate interconnection. Temperature, pressure, and surface roughness were examined and optimized process parameters are shown below. Oxidation of the copper surface is shown to hinder the bonding as is surface roughness. Samples with roughness of a few hundred nm could not be bonded.


Annealing at 400 C for 2 hours gave the best bonding results.


Kelkar of Maxim discussed their mold compound free fan out package which they reconstitute on a silicon wafer.

In order to avoid the issues inherent with mold compound based fan out wafers such as warpage, Maxim has developed a process based on silicon wafers. They list one of the packages attributes as “low cost” although I’m sure there are those who would disagree. The process flow is shown below.

Cavities are formed in the silicon wafer by wet etching, die are placed face up in the cavities and the remaining space filled with epoxy. RDL and ball placement follow similar to other FOWLP chips first approaches. It is shown in cross section below. The parts have passed std WLP reliability testing.



Asahi Glass

Nomura and co-workers from Asahi Glass discussed CTE controlled glasses for the minimization of thermal stresses in package formation and assembly. In order to minimize the stress induced on silicon during thermal processing glass substrate are required to be perfectly matched to silicon over the required temp range. Asahi glass claims to have developed such a glass “glass C” as shown below.

Asahi glass 1

Glass C is an aluminoborosilicate composition with controlled chemical composition and thermal history. Silicon wafers bonded to this CTE matched glass show very low warpage over the required temp range.

Answer to IFTLE 313 question:

The “rock” on the right is none other than the island of Manhattan, built on a giant slab of mica schist. The photo was taken from 10k+ feet, at night, by my younger son Christopher who is a Chef in Maine. Old time IMAPS members might remember Christopher attending the IMAPS Ogonquit MCM workshops run by Jack Balde 20+ years ago.

If you swing the picture around so that the pointy end is in the top right corner, Times square is the bright area in the lower left.

An IFTLE technology tidbit is that my neighborhood (Hells kitchen which is just west of Times Square towards the Hudson river) was one of the first neighborhoods in NYC to be electrified (well before I was born). Recall Thomas Edison’s method for generating and transmitting electricity was called direct current (DC). Westinghouse Electric purchased the “polyphase” alternating current (AC) system invented by Nikola Tesla. In an AC system, transformers are used to step up, the voltage that leaves the power plant which enables electricity to travel over long-distance wires. When the electricity reaches its destination, another transformer would then step down, the voltage so that power could be used in homes and factories. There was a major commercial battle to see what technology would win.

My father told me that our neighborhood was initially fitted with the Edison DC system and ran that way through the early 1930’s before it had to be retrofitted with the less costly and more reliable Tesla system. I’m sure at the time everyone thought going with the Edison system was the safe and sensible thing to do, but sometimes it isn’t.
For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 313 IMAPS 2016 Part 2: JCET & Qualcomm Discuss CPI for Die in FOWLP

By Dr. Phil Garrou, Contributing Editor

Post Thanksgiving IFTLE mean an update on Maddie (L) and Hannah (R). The family spent Thanksgiving in NYC where I grew up. The rock behind them is from the meteor exhibit at the Museum of Natural history. Speaking of rocks, can anyone identify the rock on the right?

H & M


Lin of JCET discussed CPI (chip package interaction) for 28nm die in eWLB fan out packages. JCET proposes FOWLP as the 3rd wave of packaging:


They proposed the following current and future eWLB solutions:


They have evaluated electrical CPI and CBI (chip board interaction) for their FOWLP technologies with the following test package and found no problems.

jcet 3



Ray of Qualcomm examined CPI (chip package interactions) in FOWLP.


qualcomm 2

qualcomm 3

IMAPS 3D-ASIP in Burlingame CA DEC 13-15

Hope to see many of you at the annual 3D ASIP conference run this year by IMAPS and held at the Burlingame Marriott. Special attention was paid to bring new viewpoints on high density packaging technology. Some of the Highlight presentations include:

“Image Sensor Technology Evolution for Sensing Era” – Tetsuo Nomoto, Sony Semiconductor Solutions

“Future Landscapes for 3D Integration: From Interposers to 3D High Density” – Jean Michailos, STMicroelectronics

“3D Stacked Image Sensors from a Chinese Perspective” – Roc Blumenthal, SMIC

“Heterogeneous SoCs” – Professor Subramanian Iyer, UCLA

“3D Heterogeneous Integration of CMOS, InP, and GaN Devices Using Hybrid Wafer Bonding” – Andrew Carter, Teledyne

“Essentials of Thermo-Compression Bonding” – Hugo Pristauz, BESI

“ Extreme Wafer Thinning to 5 µm for Low Cost Via Last” – Dave Thomas, SPTS

“Chiplet Partitioning for 3D Many Core Architectures” – Denis Dutoit, CEA-Leti

For full program details and registration see:

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 312 Mergers, Acquisitions and Rumors; IMAPS 2016

By Dr. Phil Garrou, Contributing Editor

Before we take our first look at IMAPS 2016, let’s first look at some recent merger announcements and rumors which continue unabated.

ASE / Siliconware

Despite the recent approval by Taiwan’s Fair Trade Commission the proposed merger between ASE and SPIL continues to be reviewed by anti-trust authorities in China and the US. It is reported that it is unlikely to gain approval from the two major markets until the end of 2017. [link] ASE and SPIL agreed to merge through the formation of a parent holding company. The holding company would own ASE and SPIL.

The merger would create the world’s largest IC assembly & test company and widen the market gap with rival rivals such as Amkor China-based Jiangsu Changjiang Electronics Technology (JCET).

Earlier in 2016 Digitimes reported rumors that Amkor is being targeted for acquisitionby China’s Nantong Fujitsu Microelectronics (NFME). NFME previously acquired an 85% share of AMD’s backend operations in Penang, Malaysia and Suzhou, China for $371 MM.

Qualcomm / NXP

As we discussed in IFTLE 306 [“Qualcomm acquisition of NXP ?…”] , Qualcomm agreed to acquire NXP Semiconductors for $38.5 billion. This will give Qualcomm a presence in the chips for smart cars market.

Siemens / Mentor Graphics

Siemens and Mentor Graphics announced that they have entered into a merger agreement under which Siemens will acquire Mentor for $4.5B. Siemens is acquiring Mentor as part of its Vision 2020 concept. Mentor is expected to complement Siemens offering sin mechanics and software with design, test and simulation of electrical and electronic systems. Mentor is generally viewed as a global leader in IC design, test and manufacturing; electronic systems design and analysis and automotive electronics. The deal will boost Siemens software revenue by about a third.

Samsung Electric to acquire Harman International

Samsung Electric has announced it will acquire Harman Int for $8B. Harman is best known for making car audio systems such as Harman/Kardon and JBL. Samsung’s interest is in Harmans “connected car” business which supplies navigation services, onboard entertainment systems and connectivity to the rest of the world.

Rumors from Asia

IFTLE hears that silicon interposers are still in short supply. Word is that Inotera has backed out of the business before they ever entered it. Recall ASE announced Inotera would be their supplier [see IFTLE 187 “…..ASE / Inotera 3DIC JV”]. So who will supply ASE now? Have they decided not to be a player in this market sector ?

If we look at who is really supplying, i.e. actually selling, silicon interposers (vs the lists put together by marketing companies that are pages long and include everyone who wants their names included) we are left with TSMC (per their CoWoS technology) and UMC who is supplying AMD. As Porkey Pig used to say in the cartoons I used to watch as a child “That’s All Folks!”

Porky Pig

Is there any wonder why 2.5D is struggling to take off with only these two suppliers in the infrastructure?

Congratulations to “Doug” Chen Hua Yu – TSMC

Doug YuRumor from Taiwan is that TSMC’s Douglas Yu was promoted to VP based on the success of InFO. Note that Doug was also responsible in a large part for the commercialization and success of CoWoS. As IFTLE has stated before, Doug, who earlier in his career was responsible for on chip interconnect scaling, was moved to packaging and has been a real driving force there.

Rumors persist that TSMC will license their InFO technology to 1-2 OSATs when their current fab is near sold out. IFTLE hears that Amkor is pursuing this licensing aggressively.

IMAPS 2016

The IMAPS 49th Int. Symp. on Microelectronics was held in Pasadena CA in October. For the next few weeks we’ll be looking at some of the key presentations from that conference.


Amkors Huemoeller certainly gave toe most relevant keynote “Creating Semiconductor Value through Advanced Packaging”. Nothing could be more in line with the theme of IFTLE for the past 6 years than the focus in the semiconductor industry shifting from the front end to packaging.

Huemoeller points to the fact that tier two OSATS simply do not have the scale or liquidity to invest what is needed to stay on the leading edge. He indicates that an investment of > $500MM / yr is required to just sustain current business.

**Remember the IFTLE credio “The leading edge is where you make the money” **

– investment in leading edge technologies creates scale and drives down costs.

He puts fort the following industry segments as driving packaging technology.

Amkor 1

And lists the following as the “Big 5” packaging platforms:

Amkor 2

– WLCSP is now showing > 30% penetration in high end smartphones.

We all know about the sensors in smartphones , but probably not the extent of sensors coming in automobiles:

amkor 3

Amkor 4SiP are basically today’s generation of what we used to call Multichip Modules in the 1990s. Amkor sees them requiring state of the art technology and driving heterogeneous integration with and without sensors.


Huemoeller sees the next gen of MCMs (or SiPs) being wafer based, since they will provide the best performance (power, electrical and thermal) and the thinnest form factor.

The following chart show how they see fan out packaging evolve into advanced SiP.

Amkor 5

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 311 SEMICON Taiwan Part 5: Packaging at TSMC

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 Semicon Taiwan. This week we finish our overview of Semicon Taiwan 216 with an examination of presentations by TSMC who as we all know is making a major push into the high end packaging market.

TSMC – Packaging Solutions

Doug Yu discussed TSMC packaging solutions which are summarized below:


The history of TSMCs CoWoS interposer commercialization is shown below. CoWoS “key merits” include:

Sub-mm interconnect

  • DD Cu, 1000+ lines/mm
  • Small via, easy routing
  • Very low defect density

Super large size

  • 1200 mm2 in production. Going 1500 mm2
  • Highest level of multi-die integration


Multichip InFO vs multichip FC CSP are compared below:


TSMC – Interposers Past, Present and Future

Shang Hou of TSMC discussed interposers past, present and future.

Hou compared the TSMC CoWoS TSV based interposer technology to TSMC InFO fan out packaging in the slide below. The first gen CoWoS started in 2012 with 28nm logic chips. The industry’s first 16nm network processor was built with CoWoS® in (2014). CoWoS delivers faster time-to-market by eliminating the node-dependent CPI seen in conventional packages.

TSMC Hou 1

2nd Gen CoWoS

The industry’s first 20nm FPGA product was built on CoWoS in 2015

  • xtra large interposer ~1200 mm2
  • Composed by two-masks stitching of sub-micron RDL
  • Package with record-large chip size
  • Passed stringent component reliability tests

TSMC Hou 2

Volume is by far the No.1 factor in the cost equation

  • It has not yet find a niche in mobile applications
  • There is firm demand in the extremely high-end market (Cloud)

Interposer high intrinsic cost is unavoidable compared with flip chip. The key is whether it has sufficient value to justify the cost?

For all the latest on Advanced Packaging stay linked to IFTLE…



IFTLE 310 SEMICON Taiwan Part 4: TSV Based Packaging – SPIL, Amkor, EVG

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week let’s look at some presentations that focused on TSV based packaging.

SPIL – TSV in IC Packaging

Mike MA of SPIL reviewed the status of TSV in IC Packaging. His summary of current TSV usage is shown below:

  1. TSV in CIS – Sony
  2. TSV in MEMS/Sensor
  3. 3D IC with TSV – only in High Band Width (HBM) DRAM

-Hynix, Samsung start HBM-1 LVM in 2015

-HBM-2 in 2016

– Advantage proven, cost still high

  1. 2.5D IC with TSV Si Interposer

– 2010 Xilinx debuted 1st product group (FPGA)

– 2015: AMD rolled out 2nd product group (GPU+HBM)

– 2016 nVidia GP100 with HBM-2

– Renewed interest for high end networking, VR/AR

SPIL currently doing 40um pitch on their ubumps as shown below.


SPIL is a proponent of the so called “chip on wafer last” process flow as shown below:



Other interesting comments by Ma include:

“The glass interposer has come and gone due to a lack of ecosystem”

“Fine line organic interposers keep delaying delivery of 5um L/S with still unknown costs. PCB insustry needs to invest in sub 5um L/S”

“Fan out packaging is capable of 2um L/S x 2 layers, but larger package size (> 15 x 15mm sq) will be challenging”

Amkor – Large Die Assembly with TSV Packaging

JY Khim discussed large die assembly technology in TSV packages. He notes the following points about their multi-die platforms:

CoS Process Flow

  • No molding                 • Interim test available
  • Mold sensitive components OK   • Shared infrastructure with FCBGA

Initial interposer warpage affects the PCB + interposer warpage. For the successful top die attach warpage minimization of interpose is important. Tuning the Inorganic C4-side passivation layer can reduce interposer warpage.

Amor Khim 1


He compares the CoS to the CoW process below:

Amkor Khim 2

In the CoW Process, there are no warpage risks in top die attach on interposer regardless of die size.

Khim showed the following table containing Amkor 2.5D CoW experience.

Amkor Khim 3

EVG – Chip Stacking in High Volume

For those looking for a good comparison of Samsung vs Hynix stacked memory cross sections, Wimplinger of EVG offered us the following figure and table comparing the two.


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 309 SEMICON Taiwan Part 3 : Fan-Out Technologies; Amkor, K&S & Yamada

By Dr. Phil Garrou, Contributing Editor

Continuing our look at advanced packaging activity at the 2016 SEMICON Taiwan. This week, let’s look at some interesting presentations on fan-out packaging.

Amkor – Fan Out Solutions for Today and Tomorrow

Ron Huemoeller of Amkor addressed the status and future of fan out solutions. Amkor expects 2B fan out packages to be shipped this year.

Traditional WLFO applications and drivers are shown below.

Amkor 1

Huemoeller reports that advanced Fan Out offers the following value proposition:

– reduced Z height and form factor           – enhanced signal integrity

– superior impedance matching                 – optimized power distribution

– improved thermal performance/junction temp

– ability to address multi die heterogeneous integration (i.e. SiP)

Traditional fan-out is reportedly gaining momentum in mobile market, i.e. RFIC, CODEC and PMIC

The table below shows their assessment of Amkor Advanced fan-out (SWIFT) vs FC CSP solutions.

Amkor 2


They see advanced FO (i.e SWIFT and TSMC’s InFO) being used in mobile applications such as

– Apps processor               – Baseband (logic + memory)

– power management     – display driver SiPs

Right now they claim that traditional fan out has cost parity with FC CSP at 0.5mm die size.

K&S – Equipment Selection for Fan-Out Process Flows

Strothmann of K&S detailed considerations to make when determining equipment for fan-out process flows.

  • Past and current FOWLP is typically the Infineon eWLB variety but also can be Motorola RCP or Deca versions.

– Lower I/O count devices

– Mostly single die, some multi-die and a few die with passives

– applications include Baseband, Power Management, RF, Analog, Bluetooth

  • High Density FOWLP is expanding rapidly

– Competing technologies in an unsettled market space

– High density I/O capable

– Application Processors, Memory, Multi-die Si Partitioning, Heterogeneous Integration

  • Wafer vs Panel formats are also being examined

Strothmann notes the following FOWLP process flows in HVM today:

  • Face Down, Die First: Typical Infineon licensed eWLB process, highest volume
  • Face Up, Die First: Similar to flow used by TSMC and others, HVM potential
  • Face Down, Die Last: Similar to Amkor’s SWIFT or SLIM process
  • Accuracy and UPH are Key Metrics for equipment selection in all flows

K&S 1

  • Face down typically has the highest position shift but also has the highest UPH (lowest cost)
  • Face up die placement accuracy can be improved with application of heat and force to lock die position
  • RDL first allows for high accuracy due to metallurgy and die position being locked prior to reconstitution

FOWLP manufacturing today is primarily driven by a round 300mm format.

Panel format requires new processes and equipment to be developed

– Panel size has not been set as an industry standard

– Maximum panel size appears to be 650x650mm but many potential smaller sizes

– Difficult for equipment suppliers to prepare

– Immediate TAM is quite low due to die volume per panel

  • Panel lines require significant loading for full utilization
  • Larger package size is required to drive panel volume (SiP, IoT?)
  • Adoption of mainstream panel processing remains a few years out

Strothmann suggests the following equipment selection criteria by process flow:

K&S 2

Yamada – Wafer Molding for Fan-out Packages

Katsuyama-san of Yamada discussed wafer molding systems for fan-out packaging. Yamada has been around since 1953 working on standard lead frame packaging.

Yamada 1

Their fan-out assembly process flow giving 5 sided protection is shown below. This is achieved by cutting grooves into the wafer isolating the components and backfilling them with molding compound as shown below:

Yamada 2

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 308 SEMICON Taiwan Part 2: Laser Processing for WLP; IoT in the Post-Smart Phone Era

By Dr. Phil Garrou, Contributing Editor

Continuing our look at Advanced Packaging in SEMICON Taiwan 2016.

AMKOR – Lasers for the Manufacture of WLCSP

WL Huang of Amkor examined the use of lasers in the manufacture of WLCSP (fan-in WLP). As we all know by now Huang pointed to size, weight, cost and performance as the drivers for WLCSP.

In the following chart, Huang shows that the same 7.6 x 7.6mm chip with 28 I/O saves a lot of real estate when packaged in a WLCSP and that the bulk of such fan in WLP are projected to be for analog and mixed signal devices.

amkor 1

The main applications for laser in WLP are:

Laser marking

  • Scribe product info on die backside for traceability

–Laser dicing

  • Separate product from wafer form to die form

–Advanced process node low-k wafer (90 nm and below). Delamination can be easy observed by blade saw due to low-k material being more brittle

–Saw street design issues – reduce topside chipping and peeling

–Saw street width shrink – By shrinking saw street width, gross die per wafer would be increased which can reduce unit cost, ex. RF switch, LNA products

amkor 2

Two kinds of laser cut can support saw street width down to 20 μm: Stealth dicing (SD) and full laser cut.

The stealth dicing process is shown below:

amkor 3

The key to full laser cutting is minimizing the HAZ (heat affected zone).

Amkor 4

ITRI – Emerging Trends & Apps for IoT

Ray Yang of ITRI examined the “Emerging Trends and Applications of IoT in the Post Smart Phone Era”. This presentation started with two interesting slides depicting Taiwan’s electronics revenue.

2014 Semi industry ranked first in value-added among Taiwan’s manufacturing sectors. The foundry business contributes the most to the Taiwan IC industry as shown in the breakout below.


Taiwan IC packaging and test accounts for more than half of worldwide assembly and test revenues.


When examining the future of autonomous vehicles he broke out the requirements into the 3 functions: sensing, understanding and action as shown below.


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 307 Micross Acquires RTI Int Fab & Personnel ; Teledyne Heterogeneous Integration with Ziptronix DBI; Semicon Taiwan part 1: Market Trends

By Dr. Phil Garrou, Contributing Editor

Micross Components Acquires RTI Int. Fab and Packaging Group

Micross Components of Orlando, FLA announced the acquisition of RTI International’s Microsystem Integration and Packaging group and fab in Research Triangle Park, NC. Some of you may recall this RTI site as The Microelectronics Center of NC (MCNC) in the late 19080s through early 2000’s.

Micross is a provider of bare die and wafers, custom packaging and assembly, component modification services, electrical and environmental testing to manufacturers and users of semiconductor devices. The 35 year old company serves the Defense, Space, Medical, Industrial, and Fabless Semiconductor markets.

This acquisition brings the RTI wafer bumping, 2.5D/3D packaging and interconnects technologies to the hi-reliability electronics platform of Micross. Micross plan is to expand its capabilities to serve customers in the defense and medical electronics sectors with these newly acquired advanced packaging technologies.

The Micross “Advanced Interconnect Technology” ( AIT )” team will be led by VP Dr. John Lannon , Director of Operations Rex Anderson and Director of Engineering Alan Huffman.

The financial details of the acquisition were not revealed.

Teledyne Details Heterogeneous Integration using Ziptronix DBI

In IFTLE 303, we indicated that Sony was using the Ziptronix DBI process in their image sensors for the Samsung Galaxy S7 [link]

We have recently discovered that Teledyne, under the DARPA DAHI program, has demonstrated 3D integration of high- performance compound semiconductor devices and Si CMOS using similar technology. Teledyne’s Miguel Urteaga indicates that “… Adding the complexity and integration density of CMOS to Teledyne’s ultra-high speed Indium Phosphide bipolar transistor process enables new classes of mm-wave and sub-mm-wave electronics for future DoD and commercial applications” A cross-section is shown below.



Over the next few weeks we will review some of the highlights of the recent Semicon Taiwan Conference. This week we will look at the “market trends” forum moderated by Elizabeth Sun of TSMC.

Handel Jones – Int Business Strategies 

IBS projects the Semiconductor market to decline in 2016. He market broken out by product type is shown below:



IBS projects that 3D NAND flash will overtake 2D NAND Flash in 2018. 64 layers should be in volume production in 2017. Samsung appears 12-18 mo ahead of its competition.



Wafer fab activity in China shows a strong emphasis on memory as shown below. However Chinese DRAM vendors are not expected to have a large impact on supply before 2020.


Dan Tracy – SEMI Equipment & Materials Outlook

Of the 21 fabs beginning construction, 11 will be in China.


200mm capacity is expanding with 8% growth expected between 2015 and 2019.

The wafer materials forecast is shown below:


The packaging materials forecast is shown below. “Other” includes solder balls and WLP dielectrics.


A key factor here is that laminate based substrates will begin to feel the pressure of FOWLP packaging as they take market share.  

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 306 Qualcomm Acquisition of NXP?; HBM IP at Open Silicon; IEEE 3DIC Program

By Dr. Phil Garrou, Contributing Editor

Qualcomm Negotiating to Acquire NXP

Long time readers know that IFTLE has been following the consolidation in our industry for more than 8 years now based on the basic laws of economics telling us this was going to happen. [see IFTLE 241 “Simply Obeying the Laws of Economics”]

Reports from multiple financial sources indicate that NXP Semiconductors has hired an investment bank to help them deal with recent acquisition offers. Qualcomm is viewed as the likely acquirer. According to the Wall Street Journal (WSJ) the deal would be worth over $30B. [link]

Qualcomm and NXP both supply Apple. Qualcomm apparently has its eye on NXP’s position in the automotive supplier business based on its Freescale takeover in 2015. The automotive chip business will reportedly show above average future growth.



Bloomberg reports that others who could possibly jump in with bids includes Broadcom, Intel and Samsung [link].

According to the WSJ, the deal would reshape Qualcomm. While Qualcomm currently derives most of its revenue from designing and selling chips, the company earns more than half of its profits from licensing its wireless patents to nearly all makers of mobile phones.

HBM IP at Open Silicon

TSMC’s Open Innovation Platform (OIP) Forum was held Sept. 22nd at the Santa Clara Convention Center.

A recent discussion on Semiwiki [link] by Tom Simon indicated that Open Silicon discussed their IP for HBM memory stacks on 2.5D interposers at the meeting.

This topic is discussed in detail on the Open Silicon web page [link].

Open-Silicon’s subsystem IP solution comprises the HBM Controller, PHY and 2.5D interposer IO addressing interoperability and 2.5D design, test and SiP packaging challenges. The HBM IP claims to be suitable for graphics, high-performance computing, high-end networking and communication applications that require low power and small form factor.

Open SI 1

Open-Silicon claims their HBM IP is the industry’s first solution for integrating HBM into ASICs for high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. The Open-Silicon HBM IP fully complies with the HBM-Gen2 (2 Gbps per signal) JEDEC standard.

Back to the OIP presentation, Simon reports that Open-Silicon has implemented an HBM reference design in 16nm. According to Open Silicon 16 nm FinFET is the key to unlocking the full benefits of HBM since it can potentially reduce power and boost performance by 50% relative to 28 nm.

In the current design Open Silicon replaced (24) DDR3 1600 with 1 HBM stack, the power consumption went from 1.0 mW /Gbit to 0.33 mW. The data rate climbed from 4 GB/s up to 256 GB/s.

OpenSi 2

To effectively shield the 0.85 um signal lines from cross talk, ground wires of 0.5um were placed 2.1um to the side of each signal wire. This left 2.1 um for each signal line.

IEEE 3DIC Conference


ieee 3dic


The IEEE 3DIC conference, which I helped put together several years ago, is back in SF this year and will be held Nov 9 – 11th. [link]

Topics will include:

– 3DIC Processing                            – Design and Applications

– Thermal Analysis                           – Bonding

– Reliability and Stress                  – Power & Signal Integrity


Next week we will start our coverage of SEMICON Taiwan packaging activities. For all the latest in Advanced Packaging, stay linked to IFTLE…