An SoC alternative offers miniaturization, enhanced electrical performance and greater interconnect density.
BY KEVIN RINEBOLD
Over the past few years, multichip module (MCM) technology has experienced a rebirth of sorts, in the form of few-chip packages (FCPs). Increasingly, companies are embracing FCPs for technical and business reasons. These FCPs are visually indistinguishable from their single-chip brethren, and are a radical departure from the MCMs of the early 1990s. Instead of something with two dozen die, today's FCPs typically contain two to four die mounted on a laminate substrate in a ball grid array (BGA) package. This “rebirth” can be attributed in part to improved bare die testing and handling, along with the availability of low-cost, high-performance laminate substrates. Furthering their acceptance is the growing trend to use FCPs as an alternative to system-on-chip (SoC) approaches, resulting in a system-in-package (SiP) solution.
The System-on-chip Alternative
Semiconductor manufacturers using the latest processing technology can now produce devices with tens of millions of gates on a single piece of silicon. Chip designers no longer worry about gate count, but are instead concerned with how efficiently they can take advantage of all the gates available. With shrinking product life cycles and time-to-market pressure, it is no longer practical to design complex integrated circuits (ICs) from scratch. Many device manufacturers are using pre-designed blocks of circuitry, which are often the intellectual property (IP) of another company. The use of IP blocks is one of the primary enablers behind SoC, in which circuitry from different sources are married into a single-chip solution.
While the performance potential of SoC is compelling, this approach has been difficult to implement in many applications. An SoC design may require IP blocks from different vendors using different processes. Consider the challenge of combining a microprocessor core designed for a 0.25-micron process, with a switch or memory core designed for a 0.18-micron process. Other semiconductor technologies, like gallium arsenide (GaAs) and silicon germanium (SiGe), can also complicate the SoC equation.
The availability and cost of the IP block must also be considered. Some applications may require the use of high-performance IP blocks (such as DRAM or RAMDAC) that only a small number of silicon foundries can implement, resulting in a difficult pricing model or, worse, a single-source scenario. For fast-paced dynamic markets where design flexibility is crucial, silicon integration may simply be too expensive and slow.
Table 1. Comparison of few-chip package (FCP) and system-on-chip (SoC) considerations.
An alternate approach to IP reuse without the business and technology headaches of SoC – but with many of the same benefits – is few-chip packaging (Table 1). In an FCP approach, the IP blocks are implemented in their respective bare die format and combined on a high-performance substrate. Many semiconductor and systems manufacturers are now using FCPs as a means to manage risk and deliver new products to the market sooner.
Benefits of FCPs
Semiconductor manufacturers are increasingly finding themselves in the printed circuit board (PCB) world because of the growing impact that the PCB has on device performance. Vendors are now selling chip sets that include detailed documentation specifying relative component placement, layer stack-up and restrictions for board layout to achieve optimal performance. When customers complain about chip set performance, it can often be traced to the PCB layout not complying with the vendor's recommendations. By providing the chip set in an FCP, the vendor has more control over the performance of its chip set in the customer's system. FCPs also use less board space, require fewer I/Os and consume less power.
Using an FCP for the chip set greatly reduces the board area required. Interconnect lengths between devices in an FCP are significantly shorter because of the close proximity of the die to one another. Reduced interconnect delay, less cross-talk, lower capacitive loading and the ability to use lower power I/O drivers on the die are direct results of the shorter lengths.
Chip set manufacturers also use FCPs as a means to localize high-bandwidth, high-speed busses, resulting in fewer I/Os at the board level. With bandwidths in the range of 1 GB/s today – increasing to 100 GB/s in the near future – these busses are becoming increasingly difficult to implement in current PCB technology. Using FCPs for these faster and wider busses makes it cost effective to use high-performance laminate substrates that offer greater trace density and lower dielectric constants. The shorter interconnect length in an FCP results in fewer power and ground pins needed to manage parasitic capacitance and inductance brought on by the faster switching speeds.
One challenge facing SoCs that is easily addressed by FCPs is combining mixed technologies like SiGe and GaAs. Because bare die are used in FCPs, mixed technology devices can be combined regardless of process technology. The FCP approach also supports the use of surface mount devices or discrete chip capacitors and resistors alongside the bare die.
Managing Business Risk
To further justify the FCP approach, there is also the business case of using FCPs as a means to manage risk and speed up product introduction. While SoCs may deliver ultimate performance, FCPs may sometimes be the only practical way to combine IP from multiple sources or incorporate mixed semiconductor technologies. FCP presents an attractive risk management strategy when time to market and acceptance is paramount, as is the case in competitive markets like the graphics chip segment.
Companies that succeed in the graphics market have done so by using FCPs as a means to capture design wins. Next-generation products that require use of IP from multiple sources can easily be prototyped and demonstrated in FCP form, which buys time for development of the longer lead-time SoC solutions. FCPs afford manufacturers the ability to introduce derivative products rapidly across a performance spectrum. By mixing the graphics processor with varying amount of memory or other functions within an FCP, solutions for a variety of platforms and price points can easily be introduced. FCPs also allow the introduction of pin-compatible products.
Demand for wireless communication, digital consumer and Internet infrastructure products are the market drivers responsible for FCPs, but advances in laminate substrate technology and bare die testing and handling are the primary factors responsible for their success where MCMs previously failed.
One shortcoming of MCMs was that as more chips were added to the module, the potential defect density grew exponentially. While the same could be said for FCPs, a pragmatic design philosophy using just a few chips combined with better testing methods has been the difference. With two to four chips in a package, reliability engineers can predict the yield of the FCP based on the reliability data of each die. Additional wafer-level testing is usually available at a small premium.
Figure 1. This four-chip FCP design was created using software for advanced IC package design. (Photo courtesy of Amkor.)
Significant advances in laminate substrate technology, such as sequential buildup, low dielectric constant materials and microvias, have facilitated commercial use of FCPs. Because FCP substrates are significantly smaller than conventional PCBs, it is more economical to localize high-bandwidth interconnect to an FCP and pay the premium for the increased wiring density for only that part of the system. Implementing the high-bandwidth interconnect using conventional PCB technology would require increased board area and layer count, driving board cost past the premium of the high-density substrate in the FCP (Figure 1).
Moisture absorption in laminate substrates has long been a barrier for their use in harsh environments, such as automotive applications. The newer laminate materials and processes can now meet the moisture saturation standards of these harsh environments, enabling their use in applications traditionally dominated by ceramics.
FCP Design Considerations
The number and complexity of chips in an FCP affects package performance and creates numerous design decisions and trade-offs. How many chips should be in the package, and which ones? Should they be mounted using wire bonding or flip-chip? Can the design be routed in the targeted layer count? What signal integrity issues will be encountered? Is the design outsourced or done in-house? These are just a few of the questions when implementing FCPs. Unfortunately, many traditional package design tools lack the necessary functionality to quickly evaluate or implement these trade-offs.
Implementing FCPs requires design software that is easy to use and provides the dedicated functionality needed for advanced IC packaging, including flexible die import, wire bonding, high-density automatic routing, and interactive trace editing. Analysis functionality to evaluate electrical performance and manufacturability should also be included.
For most FCP designs, wire bonding is more economical than flip-chip, and standard automated wire bonding methods can be used. However, most wire bonding equipment is optimized for single-chip packages, so care should be taken placing the chips within an FCP so that there is enough clearance for wire bond tooling.
FCP design software should provide online rule checking that continuously monitors manufacturing constraints to ensure compliance. Design software should allow fast wire bond generation and editing that is capable of supporting multiple rings of substrate bond pads. While most design tools provide wire bond functionality, some lack flexibility and speed, which limits the number of options that can be evaluated efficiently. The ability to quickly evaluate several wire bond patterns provides early insight as to whether the wire bond pattern can be assembled.
Substrates in FCPs typically have four to six layers and often include dedicated voltage layers for enhanced electrical performance. Routing these designs involves moving from the I/O pads on the die out to ball pads on the array. The resulting interconnect tends to be non-directional and more flow oriented, running diagonally on some portions of the layer. This is a radical departure from PCBs, where horizontal/ vertical trace predominance is established and alternated on adjacent layers. Because of the smaller substrate area and close proximity of devices in an FCP, the concept of establishing directional predominance doesn't work for FCPs.
While much of the automatic routing technology developed in the late 1980s through the mid 1990s is still viable today, much of it relies on the concept of directional predominance. Even though FCPs contain fewer components and connections, the routing challenge they present is more complex than what most PCB auto-routers can address due to the non-directional nature of FCP interconnect.
Automatic routing of an FCP requires new technology that is capable of routing at any angle on a given layer. FCP design tools require auto-routers that use non-directional algorithms capable of producing dense, all-angle routing results for FCP designs.
Because one of the primary reasons for using FCPs is to localize high-speed, high-bandwidth interconnect, early electrical analysis of the layout is critical. Performance contributors like timing, crosstalk and electromagnetic interference (EMI) must be evaluated and managed.
Electrical analysis of an FCP early in the design cycle can reveal problems easily corrected before design completion. For example, finding a simultaneous switching problem due to noisy lines can be rectified by inserting additional power and ground connections, a task that is easily completed while in the design process but not once the design is complete.
FCP design tools should include integrated electrical analysis capable of predicting signal integrity, crosstalk, and EMI problems. To manage and explore solutions for performance problems, functionality to control net topologies, termination strategies, layer stack-ups for impedance control and routing constraints should also be included.
While MCMs never achieved commercial success, much of their performance value has been realized in FCPs. Miniaturization, enhanced electrical performance and greater interconnect density are the goals of FCPs, just as they were for MCMs.
Using an FCP as an alternative to an SoC can provide a more economical and practical approach to combining IP from multiple sources or mixed semiconductor technology. Because FCPs can be implemented much more quickly than SoCs, it is an attractive risk management strategy. Implementing FCPs requires specialized design tools capable of addressing their unique design challenges. The design tools should enable the user to optimize performance and cost of the isolated functions in the FCP design, as well as the overall system performance.
For more information, contact Kevin Rinebold in product marketing, advanced IC packaging, at Avant! Corp., 177 Victor-Heights Parkway, Victor, NY 14564; 716-742-8403; Fax: 716-924-4729; E-mail: Kevin_Rinebold@avanticorp.com.