Dec. 2004 Exclusive Feature:

New vertical collaboration, government help called for at Nanotech Conference

By Bob Haavind, Editorial Director

New materials and process complexity require increased R&D, but available resources at process tool companies are being squeezed. As a result, new collaborative models will be necessary to meet future challenges to stay on the track of Moore’s Law, Mike Splinter, president and CEO of Applied Materials, told more than 200 attendees from around the globe at the Albany Symposium on Global Nanotechnology, held in Sept. at Lake George, NY.

Strapped tool vendors are spending a steadily smaller percentage of revenues compared with chipmakers on process R&D, Splinter said, because of a number of forces in the industry. The wafer-size transition requires tool companies to have dual tool-development programs for 200mm and 300mm tools.

In addition, while some chipmakers aggressively push even below-Roadmap targets, the majority continues to manufacture less advanced chips, creating a bifurcated tool market. This split means that, to be successful, a toolmaker must meet the needs for the most advanced processes, but it will take much longer to get the payback for that R&D. At the same time, end markets are shifting more to the consumer sector, pressuring chip prices and margins for the IC makers.

“A few years ago you couldn’t buy a good PC for $1000, now nobody wants to pay $1000 for a PC!” Splinter said. He also pointed out that the trend in electronic systems is away from print toward graphics, requiring higher-performance chips, while pricing power has been eroded.

So chipmakers push these declining margins down the supply chain, leaving less resources for process development, according to Splinter. He suggested that the tool industry, with some 20 large players and many more small companies, is highly competitive, discouraging collaboration, especially when development for specific processes would not be pre-competitive R&D. While more consolidation might help, he feels that there must be increased collaboration between chipmakers and tool vendors to develop future processes. In response to a question from the audience, Splinter said that materials companies also would need to be integrated into these collaborative efforts.

“R&D must become more efficient, with less duplication of effort,” Splinter suggested. He pointed out that technologies such as strained silicon, which needs to be “tuned” for different applications, and gate stacks with new high-k insulating materials are areas where collaboration will be needed over a number of Roadmap nodes.

Splinter said that struggling toolmakers had turned to outsourcing to try to turn fixed costs into variable costs and gain efficiency.

“If it can be outsourced, it will be!” he stated, citing a list of things being farmed out, including EDA, semiconductor manufacturing, design libraries, equipment, and fab services. This is a better business model because a specialist can be more efficient, according to Splinter, so there is a steady trend away from vertical toward horizontal integration. Equipment R&D can’t be outsourced, however, so other ways must be found to improve efficiency.

He pointed out that it took some four generations to convert to copper interconnects, and many circuits still do not use copper. It has also taken four generations to move to low-k dielectrics, he suggested, and use of low-k is even less pervasive. “We need to learn to accelerate this,” through these vertical collaborative efforts, he urged. While only about 15% of wafers are now at nodes below 100nm, in two or three years perhaps two-thirds of wafers will reach this level, and the industry must learn to meet these tough performance targets cost effectively. Otherwise, Splinter said, the progress toward lower cost/function will slow down, and he suggested no company in the industry is prepared to see that happen.

Already, global alliances are spreading among chipmakers as they struggle to push processing frontiers. Splinter cited IBM as the leader in this trend, with links to Infineon, Chartered, AMD, Sony, Toshiba, and now Samsung (at least for logic). Another cluster he cited includes ST Microelectronics, TSMC, Freescale, Philips, and Hynix. Now, he indicated, these alliances need to be broadened to process tool and materials companies to accelerate scaling progress with less duplication and greater effectiveness for the R&D dollars spent.

The emergence of nanotechnology will open whole new markets, but the difficulties of harnessing molecular-scale interactions and developing manufacturable devices will take a global effort, claimed Splinter. The US should take a more active role in ensuring commercial success for nanotech, providing more than just academic progress.

Already, according to Splinter, the US has lost its edge in semiconductor manufacturing — its manufacturing base is eroding as fab capacity is being shut down faster than new capacity is being added, and this will continue into the foreseeable future. In key areas the US is no longer a player, he suggested, citing polysilicon, lithography and track systems, and flat panel displays. “Is nanotech next?” he asked.

In 2004, nanotech funding will be about equal in the US and Asia (including Japan) at $1.6 billion, and another $1.3 billion will be spent in Europe. But he sees areas of weakness in the US. He urged making the R&D tax credit permanent, and strengthening US education in science and math while making it easier for foreign students to come to US universities to get advanced degrees and then stay. He also urged nurturing of regional efforts for collaboration and for spurring competitive new enterprises.

There is a flaw in the US model for starting new technology enterprises, however, according to another presentation by Michael O’Halloran, director of technology for Industrial Design and Construction, at the conference.

He described a model for commercializing new nanotechnology products consisting of several years of R&D leading to 1-2 years for pilot plant production followed by full-scale manufacturing. As an example, he cited a company developing a product for the flat-panel display industry. First round funding allowed the company to spend $20 million a year on R&D, but then it needed $100 million to build a pilot plant and $500 million more to built a factory. O’Halloran said it would be no problem to get the $500 million from commercial lenders once feasibility was demonstrated, but that no one wanted to put up the $100 million for the pilot-plant phase.

This pilot-plant phase is where regional and federal programs might be able to give a boost to commercialization of viable products for nanotechnology in the US, where there are not national programs to foster commercial enterprises as there are in some other countries. — Bob Haavind, Editorial Director


The other SST Online Exclusive for December 2004 is China’s first 300mm fab ramps, more to follow.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

NEW PRODUCTS

KLA-Tencor announces new defect inspection systems
07/12/2018KLA-Tencor Corporation announced two new defect inspection products at SEMICON West this week, addressing two key challenges in tool and process monit...
3D-Micromac unveils laser-based high-volume sample preparation solution for semiconductor failure analysis
07/09/2018microPREP 2.0 provides order of magnitude time and cost savings compared to traditional sample...
Leak check semiconductor process chambers quickly and reliably
02/08/2018INFICON,a manufacturer of leak test equipment, introduced the UL3000 Fab leak detector for semiconductor manufacturing maintenance teams t...