Sematech identifies top technical challenges for 2006; adds transistor scaling

April 19, 2005 – Sematech has announced its top technical challenges for 2006, continuing to underscore advanced gate stack, 193nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium leaders also placed planar bulk transistor scaling on the list for the first time.

Sematech uses the top challenges to focus its resources on the most critical of ~75 projects that it maintains in key areas of semiconductor and related R&D. The Sematech research portfolio is developed by the consortium’s Executive Steering Council (ESC), in consultation with corporate managers.

“Sematech continues to remain at the forefront of semiconductor R&D, and this set of challenges reflects our commitment to that goal,” said Michael R. Polcari, Sematech president and CEO. “This list also reflects the guidance of our member companies on how to best use our skills and resources to benefit Sematech’s members and the industry. We’ll address many of these issues in collaboration with our R&D partners, including the university researchers investigating promising semiconductor technologies in our Texas-based Advanced Materials Research Center [AMRC].”

The Sematech challenges reflect the consensus of the consortium’s member companies, and are grouped below by technical area:

Lithography: immersion lithography, mask infrastructure, resist strategy, and EUV infrastructure

Frontend Processes: advanced gate stack, nonclassical CMOS, and planar-bulk transistor scaling

Interconnect: low-k dielectrics and process compatibility

Manufacturing: metrology, and manufacturing effectiveness and productivity

Environment, safety, and health

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