Lower-k dielectrics struggle toward volume production

By Bob Haavind, Editorial Director

Fabs are filling dielectrics with air bubbles, sunning them under UV lamps, and putting on caps to keep molecules in place, but after a decade of development, really low-k (k<3) still has not made it into volume production. There was plenty of hope and hoopla at the International Interconnect Technology Conference (IITC) in Burlingame, CA, June 5-8, but there was also evidence of the difficulties chipmakers are having reaching values called for in the International Technology Roadmap for Semiconductors (ITRS) for 65nm and 45nm nodes. Signals are slowed by the resistivity (R) of metal lines, which already has been lowered by the move to copper, and by the capacitance (C) of the dielectric between lines (intermetal, or IMD) and between interconnect layers. Starting with ordinary silicon dioxide with a k of ~4, developers want to push as close as they can to the optimum k value of 1 for air.

Excellent technical work reported by many design teams offered hope for solving the myriad problems of integrating low-k materials (either porous or dense) with copper, starting at the 65nm node, and moving to ultralow-k (ULK) or even extreme low-k (ELK) at 45nm. Many vendors promised to deliver solutions soon in suites, demo rooms, and show booths.

Some doubt whether porous ULK or ELK materials will be ready for the 45nm node. Chipmakers are being too aggressive at 45nm, and it will be late to market as a result, said Paul Besser, AMD fellow, at a panel organized by Applied Materials. He predicted that interlayer dielectric (ILD) with suitably high mechanical strength may reach k of ~2.3, but he doubted that capping layers to prevent electromigration will be ready for prime time. He also expressed concern about etch difficulties and the high cost of lithography for 45nm.

Process simplicity was a goal cited by Farhad Moghaden, senior VP, Thin Films Group, at Applied Materials, but he also cited a number of problem areas to be addressed to achieve scaling, conformality, and reliability. He said that new technology is needed to add mechanical strength as values are scaled; erosion and dishing must be controlled for chemical-mechanical planarization (CMP); and the combination of CMP, ashing, and etch must be layout-independent with no changes in value and resistivity, with CD control to k<5nm, 3 sigma.

While simplicity is a worthy goal, one audience member observed, none of the papers at the conference dealing with this wide range of often-interacting problems offered “simple” solutions.

Douglas Yu of TSMC claimed that his foundry would find a lower-cost approach by solving the problems of each module (etch, CMP, etc.) independently, rather than leaving them for the other modules. Besser responded that there were so many interactions in the interconnect stack (such as metal fill and residues) that the problems are very interlinked. Applied’s Moghaden suggested that cutting down interfaces, such as by finding a dielectric that doesn’t have to be sealed on the sidewall with the possibility of delamination, would be one way to achieve more simplicity.

Yu of TSMC said that problems such as electromigration and stress depend on how metal lines, and barrier and copper seed layers, are integrated. Tradeoffs must be explored and possibly hybrid processes developed. Chia-Hong Jan of Intel pointed out that the change in ILD had been postponed from the 90nm to the 65nm node, and that issues such as differing coefficients of thermal expansion would be a challenge. Robert Wisnieff of IBM added that moisture penetration also could be a problem. Jan said that it would be too late to discover reliability problems when the chips are in the field; instead, new verification techniques will have to be devised.

John Chen of NVidia, the only designer on the panel, said that he would like to see as much lowering of values as possible to speed circuits, but not at the cost of reliability or other problems, such as scratches caused by CMP. He complained that sometimes critical signal lines were severed by CMP, and he challenged the process developers to come up with better solutions. He agreed that a gradual lowering of values would be preferable to a big discontinuity that proved too tough to handle. Wisnieff suggested that too many changes would introduce a lot of variability and make the learning of the past less effective. Jan of Intel commented that a reduction of 10%/year in keff might be achievable, but he pointed out that stresses in contacts and packaging also must be considered in choosing solutions.

One bright note at the conference was the emergence of ultraviolet (UV) curing as a way to add mechanical strength to low-k dielectrics. Not only is UV proving more effective than e-beam curing, which sometimes causes damage because of high-energy electrons, it also appears to have potential to solve other problems.

Strengthening may be due to dangling methyl groups crosslinking to silicon-based molecules under UV radiation, according to Kevin Durr, curing product line manager for Axcelis, with a 50%-100% improvement for porous and 25%-50% for dense dielectrics. An example was presented at an ASM seminar by Takeshi Furasama of Renesas, in which standard SiOC was converted to high-k modulus material through UV curing to convert terminating methyl groups into network components, boosting Young’s Modulus from 10 to 21GPa, for 90nm dielectrics with a k value of 3.

The UV curing techniques came from efforts by Axcelis to extend the applications for UV technology initially used to photostabilize novolac resists after the move to chemically amplified resists. At first, according to Durr, low-k developers only were looking for mechanical strengthening, but now they see UV curing as potentially offering many other improvements, such as lowering film stress while making films more uniform, plasma resistance, and poragen removal without lowering values.

CVD tool manufacturers, including Applied Materials, Novellus, ASM, and soon TEL, are responding by adding UV chambers, according to Durr. Axcelis is instead offering a RapidCure 320FC tool using its own lamps, and it will tailor the UV radiation for particular applications, which can speed processing while eliminating harmful side effects of the broad-spectrum commercial lamps used by CVD vendors.

Durr explained that some developers are finding that by tailoring the chemical bonds to provide UV-active sites within the dielectric material, superior results and faster curing can be accomplished. — B.H.

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