By: Dr. Paula Doe, Contributing Editor
Narrowing process windows, emerging tools for statistical analysis of design, and model-based simulations of yield results may soon push designers to actually design for manufacturability, argued experts at Semi’s Strategic Business Forum in Welches, OR, May 9-11.
“The easy part is the technology,” argued Mentor Graphics’ chairman and CEO Wally Rhines. “The hard part is the infrastructure.” Model-based simulation at least enables designers and fabs to talk about the problem. Economics also have to drive some other changes, though, to make it happen.
One problem is that designers are not measured on yields, but on things like meeting schedules and profitability. Show a designer all the hundreds of places his design meets the rules but might not have optimal yield, and he’ll handle it by clicking on that convenient little “x” up in the corner of his screen to make it go away, noted Rhines.
Emerging statistical design technology now makes it possible to prioritize those few places out of the hundreds possible where making a change is most likely to prevent a yield problem, so the designer can concentrate on fixing only those places-by doing things like doubling the vias, spreading out the lines where there’s room, or adding end-cap extensions. “New tools allow you to prioritize where to fix things. They find the things close to the edge,” said Rhines. “Few are using them yet. You have to convince the designer. But statistical analysis of design would change the world. [Typically] it’s assumed the problem is the process, not the design, since you can’t say the customer is wrong-but now you can show him where the design is wrong.”
Also emerging are tools that correlate test data with the design data, mapping logic failures to the physical layout so they can focus testing on the places where the shorts are most likely to occur, as in the circuits that run close to each other for the longest distance.
“What we need are tools that make it possible for the fab to visualize the process problems to the designer. If the designer has to pay for flaws that the software shows in bright colors, he would improve,” argued Artur Balasinski, Cypress Semiconductor’s manager of technology-design integration. “The way to make our lives easier is simulation. It’s more our way of communication. We can say, ‘See, these lines bridge.’ We can’t maintain this kind of knowledge by training anymore. It has to be in the rules or decks.”
Increasing process complexity also makes these efforts to improve yield more and more necessary. Rhines argued that designers at the fabless companies won’t be able to crank out designs at 65nm as easily as at past nodes. Norm Armour, VP and GM of LSI Logic Manufacturing Services-himself in the middle of the sea change to the fabless model at LSI Logic-said fabless companies may have to start incorporating extra robustness into the design from the start to get their products made by foundries at all.
DFM will be crucial to enlarge the process window, as the industry faces systematic limited yield with the end of wavelength scaling and it may have to push 193nm lithography indefinitely, argued KLA-Tencor VP of lithography technology Chris Mack, adding that ever more APC will be needed to center the process within the smaller yield window. Mack also suggested that DFM will develop in very segmented ways. With the old smaller-cheaper-faster-better model that scaling always makes money no longer true, “The assumptions of the need to jump to the next node will change-and maybe even next year,” he argued.