TSMC lays out 65nm DFM plan

May 17, 2006 – Taiwan Semiconductor Manufacturing Co. (TSMC) has unveiled a 65nm design-for-manufacturing compliance “ecosystem” to channel DFM capabilities through selected EDA tools to TSMC’s manufacturing data format.

The unified format, encompassing lithography process check, chemical mechanical polishing analysis, and critical area analysis, aims to align DFM tools in order to enable designers to use the same DFM data file across tools from different vendors, and simplifies use, management, and updates to DFM analyses.

The DFM compliance initiative involves qualifying DFM tools to make their results consistent with TSMC’s internal results, and also emphasizes run-time performance and user friendliness. The initiative also defines a set of IP and library compliance criteria including running checks, such as DFM layout parasitic extraction, a layout enhancer, and lithography process check.

“Basically, we’ve defined what it means to be DFM compliant, and we’ve helped our Ecosystem partners to achieve that compliance,” stated Edward Wan, senior director of design services marketing for TSMC.

The DFM compliance initiative involves participation from 18 companies offering IP, library, EDA, and design expertise, including: Alchip, Anchor, Aprio, AnalogBits, ARM, Blaze DFM, Cadence, Clear Shape, Dolphin Technology, Fastrack, Global Unichip, Magma, Mentor, Ponte, Predictions, Qthink, Synopsys, and Virage Logic.

TSMC completed its first 65nm prototype runs for five major customers last October, and in April announced 65nm volume production for one customer.

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