Design rule checking (DRC) has been the gold standard in the hand-off of integrated circuit (IC) designs to the manufacturer. From the beginning, when newly developed physical verification tools automated the manual check method, a DRC-clean design was the most accurate ticket to yield. Based on a compliance method of pass/no pass, the system was simple and straightforward, giving designers a faster method of sign-off and measurable assurance for successful silicon.
But at 130nm node, DRC-clean designs began failing first silicon. At that time, it became obvious that the compliance process required more than pass/no pass. This didn’t mean DRC was no longer a valid process for sign-off; it did mean, however, that DRC would have to evolve. Robust verification tools began to do just that, managing design-for-manufacturing capabilities, such as antennae effects, stress effects, metal fill and via insertion.
But that was just the beginning of the evolution. For the upcoming nanometer nodes of 65nm and 45nm, the Calibre(r) engine is revving up for a whole new race.