Samsung touts 3D methods, multilayered dielectric in new 50nm DRAM chip

October 19, 2006 – Samsung Electronics Co. Ltd. says it has developed a 50nm DDR2 DRAM chip utilizing 3D design and multilayered dielectrics, a process that enhances performance and data storage capabilities.

Production efficiency is improved by 55% vs. a 60nm process shrink, thanks in part to use of a 3D selective epitaxial growth (SEG) transistor with broader electron channel that optimizes electron speeds, reducing power consumption and leading to higher performance. A multilayered dielectric layer (ZrO2/Al2O3/ZrO2) helps resolve weak electrical signals, and sustains higher volumes of electron to increase storage capacity.

In addition, the 50nm DRAMs use Samsung’s proprietary “recess channel array transistor” (RCAT) 3D technology, which effectively doubles the refresh term of DRAM and is a “critical technology” for enabling higher scalability in DRAM chip development, the company said.

Samsung’s new 50nm process could be applied to its DRAM line including graphics and mobile chips. Mass production is slated for 2008.

Most recent scaling announcements from Samsung, which recently ramped to mass production of 80nm 1Gbit DDR2 DRAM memory, have actually been for NAND flash devices. In September, Samsung said it created a 32Gb NAND flash device using 40nm process technologies, featuring a “charge trap flash” (CTF) architecture that “sharply” reduces intercell noise levels, and enables higher scalability to enable transition from 40nm to 30nm and even 20nm processes. And two months earlier, Samsung qualified its 65nm low-power process technology at its S1 300mm logic fab line in Giheung, Korea, and ramped to volume production of its 8Gbit NAND flash memory based on multilevel cell (MLC) architecture and 60nm process technologies, two years after announcing development of the technology.

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