DFM startup decloaks with tools, customers, design flow

November 27, 2006 – After three years of behind-the-curtain development and joint work with several customers and foundries, Clear Shape Technologies Inc. has officially launched with an announcement of two flagship products, and a DFM-aware IC design flow resulting from a collaboration with Taiwan foundry United Microelectronics Corp. (UMC).

Clear Shap, backed by $10 million in funding to date (from firms including USVP, Intel Capital, AsiaTech, and KT Ventures, KLA-Tencor’s investment arm), boasts a customer roster including UMC as well as NEC and Qualcomm, and says its technology is silicon-validated for the top three major foundries (TSMC, UMC, and the Chartered-IBM-Samsung partnership). Its management team includes a trio of top execs from Numerical Technologies, which was acquired by Synopsys: Atul Sharan (president and CEO), Yao-Ting Wang (chairman/CTO), and Fang-Cheng Chang (VP of engineering). Other top execs include Nishath Verghese, VP of engineering for design technology (he formerly led engineering for several Cadence units), and Nitin Deo, VP of marketing, business development, and international sales (from similar positions at Ponte and Magma).

“The foundation that was the basis for the contract between IC design and manufacturing has been shaken as ‘rule-based’ assumptions have steadily crumbled,” with chip performance and yield dramatically impacted by manufacturing variations, said Sharan, in a statement. For example, at 65nm, systematic variations of 3nm on a transistor gate can cause a 20% variation in delay and have a 2x impact on leakage power, the company notes. “There is a dire need for tools and technologies that reinstate designers’ confidence that their chips will achieve entitled performance and be manufacturable at high yields,” said Sharan.

Clear Shape’s first flagship product, InShape, utilizes a patent-pending, model-based, non-linear optical transformation algorithm to predict accurate silicon shapes for DFM hotspot detection of catastrophic failures and accurate eDFM analysis and optimization. The compact models encapsulate all necessary RET, OPC, mask, etch and lithography effects on both device and interconnect, and predict accurate contours for the entire chip from drawn layout in a matter of hours.

OutPerform is a silicon-correlated electrical DFM analysis and optimization product, to enable designers to optimize and control the impact of a variety of processes (lithography, mask, etch, RET, OPC, and CMP) on chip parameters. The product, which uses InShape’s silicon contour predictions for its eDFM analysis and optimization, also has a closed loop to manufacturing/foundries, the company says.

The DFM-driven IC design flow, developed over an 18-month collaboration with UMC, combines the InShape and OutPerform products with UMC technology files with encrypted DFM data to create a fast, accurate, model-based analysis and optimization approach. The tools “are welcome additions to our comprehensive DFM yield optimization offerings that now target 65nm designs,” stated Patrick Lin, chief SoC architect, system and architecture support at UMC, which expects to make the technologies available to customers later this year, with results fast enough to be used during place and route.

Using both the InShape and OutPerform tools, NEC Electronics was able to utilize our 90nm process technology much more aggressively and have a closed-loop solution to address parametric issues associated with variability,” according to Takaaki Kuwata, GM of advanced device development division, within NEC Electronics’ technology foundation development operations unit. In a statement, he added that the company expects to expand its work with Clear Shape to 65nm and 55nm designs.

Pricing for InShape and OutPerform starts at $300,000 (each), per master license, per year.

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