Intel’s 45nm demo shows commitment, confidence

by M. David Levenson, Senior Technology Editor

Intel showed off first-silicon success for its next-generation “Penryn” 45nm processor, which uses hafnium-based high-k dielectric instead of grown silicon oxide as the gate insulator and two different metals as the gate electrodes, at a press event at Intel headquarters in Santa Clara, CA, on January 25. A previously scheduled announcement that Intel’s P1266 technology had achieved first production as scheduled in 2007 would have been a significant technological milestone by itself — but revealing that the first design, first mask set, and first silicon all worked properly seemed stunning.

While Mark Bohr, Intel Senior Technology Fellow, did not reveal the exact materials involved, the fact that Intel had committed to combine two innovations (with three new materials) in mainstream products indicates considerable confidence. It turns out that confidence was built up over the year since Intel’s announcement of its 45nm SRAM test element group (TEG) chip in Jan. 2006, which was also secretly built using the high-k dielectric and metal gate technology.

Three flavors of Penryn processor chips were demonstrated live to the media: 80W chips for servers, 65W for desktop computers, and 35W for notebooks, all shipped down the night before from testing in Intel’s validation lab in Folsom, CA. Reporters were allowed to observe and operate the four desktops, which ran complicated games and video processes at about 2GHz (with fans roaring) but the laptop disappeared as soon as it was shown. Steve Smith, VP of DEG Group Operations, suggested that some later versions of the 45nm generation would have even lower power consumption (down to 5W), while others would run significantly faster than 2GHz.

Bohr claimed that this first-silicon demonstration implied a one-generation technology lead for Intel vs. its competitors, with yields improving on the same track as at 65nm and with a scheduled two-year delay (see chart below). In spite of the extra process complexity, Bohr claimed that the learning at the Oregon D1D fab went even more quickly this time. The first 45nm devices will come out of D1D sometime in 2H07, followed “a few weeks” later by Fab 32 in Arizona. Intel’s under-construction Fab 28 in Israel will be ramping the 45nm process by 1H08.

Intel CEO Paul Otellini also made a quick appearance, noting that Intel was trying to synch its product rollouts with its technology announcements in order to make its internal progress seem less esoteric to customers.

While the higher performance achieved at constant power consumption may seem just a marginal improvement, it is certainly historic for Intel to replace the grown-in-place silicon oxide gate dielectric that has been universally used for silicon transistors since Andy Grove discovered the process as a graduate student. Combining that with the replacement of doped poly gates with metal probably does constitute “the greatest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960’s,” as Gordon Moore noted in a PR quote touted by Intel. But keep in mind that this is only one of several wrenching changes to come as the industry pursues Moore’s Law through the 21st century. Intel’s go-it-alone R&D strategy may allow Intel to set the technology pace, but it may or may not prove financially tenable in the long run. — M.D.L.

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