ST tips low-power 45nm SoC results

June 13, 2007 – STMicroelectronics says it has taped out the design for a low-power system-on-chip (SoC) “demonstrator” device with a multiple threshold transistors, dual-core CPU and associated memory hierarchy. The process improves speed by 20% vs. 65nm designs or reduces leakage current by half when in operation (and by “several orders of magnitude” when in retention mode), and takes up half the silicon area. Work was done at the Crolles2 Alliance’s 300mm fab in Grenoble, France.

The low-power 45nm process incorporates 193nm immersion lithography, shallow-trench isolation and transistor stressors, advanced junction engineering using millisecond anneal, and an unidentified “very low-k” intermetal copper dielectric. Two cell libraries are available for the process, one for high-performance and another targeting low power consumption. Densities up to 1600 Kgates/sq. mm are available supporting 1.1V core supply, with 0.14-micron metal pitches and 6-10 metal routing layers.

ST claims the process has already recorded “excellent results” with “high-yield” multi-Mbit SRAM test circuits, and fully functional SRAM test circuits operating at a supply voltage of 1.1V down to 0.9V. A low-cost process variant for embedded DRAM with 3x density vs. SRAM is under development, as are a range of analog and RF IP. Digital IP modules such as MPUs and DSPs also will be provided.

Laurent Bosson, EVP of manufacturing and technology R&D for ST, noted that early access to low-power 45nm CMOS technology is “crucial” for manufacturers of wireless and portable devicemakers, particularly for next-generation 3G and 4G handheld multimedia terminals.

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