SST July 07: Samsung’s NAND Flash evolution

EXECUTIVE OVERVIEW This month’s edition of Chip Forensics by analyst Dick James delves into Flash technology, including the Samsung K9F2G08U0M 2-Gb single-level cell (SLC) Flash.

Flash technology has now become a driving force in process advancement—this year, Samsung is introducing its 50nm NAND Flash memories, and the Intel/Micron joint venture is sampling a 50nm chip. The latest ITRS roadmaps reflect this—they now recognize Flash as a distinct technology driver, with its own product generation listing.

NAND Flash products have dominated the Flash market, driven by consumer demand for huge amounts of ‘dumb’ data storage for uses such as audio and video files, for which ultimate data accuracy is not required. NOR Flash tends to be used for critical data storage such as code storage, and so the product types have separated; in a typical consumer product such the Apple iPod, NOR Flash is used for the embedded firmware and NAND Flash is used for the bulk storage of the music files.

In the last few years, we have also seen the introduction of multilevel cell (MLC) technology, allowing the doubling of data density, and we may soon see the introduction of strain engineering, which reportedly improves the retention time and read current [1].

This continuous increase in density is not just a matter of shrinking design rules and changing lithography, which are not exactly insignificant in themselves; smaller dimensions limit performance unless there are process modifications to compensate.

For example, the smaller bit-line pitches necessary for higher memory density lead to high series resistances and poor bit-line delay times [2]. Thus, as we see density increase, we see changes in chip layout and bit-line process technology.

In the case of word-lines, the degradation of the RC delay times with higher density also holds true. So far, we have not seen the tungsten/titanium/cobalt/nickel silicide transitions used in logic processes to reduce resistance; tungsten polycide is the ubiquitous material in Flash devices. In general, designers have used layout techniques to reduce the word-line length to control resistance, rather than change processing. Another consideration is the line-to-line capacitance between the word-lines [3]; adjacent word-lines can capacitively couple to a floating gate and affect its threshold voltage.

Control of the floating gate in a Flash memory cell is by capacitive coupling across the interpoly and tunnel dielectrics from the control gate, making the overlap area of the control gate and floating gate a critical feature of the design. The gate lengths of both are defined by the gate stack etch; so the width and height of the floating gate are the only parameters that can be adjusted to optimize the coupling to the control gate.

Interference due to capacitive linkage between adjacent floating gates is also an important factor [3], particularly for MLC devices for which threshold voltage discrimination has to be tighter. This is forcing changes in the word-line/word-line structure; the spacing is decreasing, so the only options are to reduce the dielectric constant (k) and/or the coupling area (i.e., the width and height of the floating gate).

Similarly, the bit-line/bit-line spacing could be critical, but in current parts the control gate folds down between the floating gates and effectively shields neighbouring gates from each other.

In the last couple of years, we have looked at a series of increasingly dense NAND Flash memory chips, and I thought it would be an interesting exercise to compare the device structures, and see what Samsung has done to solve the above challenges.

Let’s start with the Samsung K9F2G08U0M 2Gb single-level cell (SLC) Flash, fabricated in a 90nm technology. This part used a triple-well process, with one level of aluminum and damascene tungsten (W) bit-lines. Figure 1 shows cross-sectional TEM images taken through and along the word-line stack. The tapered nature of the control gate (CG) with its nitride cap hard mask, and the nitride dielectric between the adjacent word-lines can be seen. In Fig. 1b, we can see the way the control gate is folded into the gap between the floating gates to maximize the capacitive coupling and shield adjacent floating gates.


Figure Source: Chipworks

The unit cell size is ~0.04&#181m2. The W-silicided control gate is ~170nm thick, the ONO inter-poly dielectric is ~17nm thick, and the gate oxide is ~8.0nm thick. Floating gate (FG) length, width, and pitch were ~107, ~150, and ~190nm, and it was ~80nm thick [4]. In this context, we define the gate width as the physical width of the polysilicon, since that is the critical coupling dimension&#151not the transistor width, in which the poly is on the gate oxide. The design used polysilicon bit-line and source-line contacts (see Figs. 1c and 1d).

Samsung reported [5] that the process used 248nm KrF lithography, with off-axis illumination, phase-shift masking, and optical proximity correction, to optimize the conflicting requirements of the high density array and isolated patterns in the periphery.

The K9G4G08U0M 4-Gb MLC Flash was one of the first MLC parts launched by Samsung; it uses tighter voltage discrimination to distinguish four voltage states, but at the expense of more complex peripheral circuitry, and increased sensitivity to capacitive coupling between adjacent cells. However, the improvement in the overall data density makes it more cost-effective for consumer products such as the Apple iPod nano, from which we took this part.

It is a 90nm process, three-metal (2 Al + 1 W) part, with multiple wells (three or more), and a cell size of ~0.037µm2. Floating gate length and width is ~106×150nm on a ~178nm pitch, slightly tighter than the 90nm 2Gb SLC part. If we compare Fig. 2a with Fig. 1a, we can see the changes made in the cell to achieve MLC capability—predominantly oxide inter-line dielectric was used, and the floating gate thickness was reduced to ~56nm. The control gate was ~188nm thick; the ONO stack ~15nm; and the tunnel (gate) oxide ~8.6nm.


Source: Chipworks

The longitudinal view in Fig. 2b does not show as many differences; the control gate is recessed into the STI more, which should improve cell/cell shielding. Other changes include the introduction of inter-poly vias between the CG and FG polysilicon (see inset) and reducing the source-line RC delay by a switch to tungsten.

Figure 3 details the structure of the K9F4G08U0M 4Gb, 73nm SLC Flash cells. They are similar to the 2Gb device in that the inter-line dielectric is nitride, although the taper on the control gate is no longer used (193nm ArF photolithography is reported [6]). FG length is ~90nm on a ~150nm pitch, but the width is reduced, also to ~90nm.


Source: Chipworks

This allows the floating gate thickness to be more like the 2Gb part, at ~86nm, although it is now formed from two polysilicon layers. The tunnel oxide is ~7.2nm thick; the ONO stack is ~18nm; and the control gate is ~150nm. The cell size is now ~0.0225µm2. It looks as though the STI etch-back has been optimized to give a rounded profile at the gate edge, to reduce parasitic effects.

Similar to the MLC part, there are inter-poly vias between the CG and FG polysilicon (see inset), and the source-line is tungsten. The device uses etched tungsten bitlines, since the barrier layers take a smaller proportion of the volume than a damascene structure of similar width; this gives lower resistance, especially at the ~75nm line width used in this part.

The 60nm technology (Fig. 4) used for the K9G8G08U0M 8-Gb MLC Flash gives an incredible ~0.016µm2 (~125nm × ~130nm) unit cell; this represents almost a 60% area shrink from the 90nm 4Gb MLC Flash memory described above. The process is a four-metal, triple-well process, and Samsung has reported [2] that the process used 193nm ArF lithography, with off-axis illumination, phase-shift masking, and optical proximity correction.


Source: Chipworks

The floating gates have an impressive 63nm gate length on a 125nm pitch, and 50nm gate width. The ONO interpoly oxide is 15nm thick, the tunnel oxide 10nm thick, and the inter-line dielectric is oxide. Floating gate thickness is 85nm, and the control gate is 133nm. The FG is now self-aligned to the active areas, and the array STI is separately formed from, and shallower than, the peripheral STI. The control gates use bi-layer polysilicon, allowing interpoly vias.

A tungsten M0 source line is used, and the tungsten M1 bit-lines are again etched, although the bit-line contacts are now high-aspect-ratio tungsten (inset 4a). There is noticeable line width roughness (~10nm, inset 4b) at the ~60nm line width used in this part.

In the above, we have shown the changes in Samsung’s NAND-Flash cells, ranging from the 90nm to the 60nm process generations. The reduced pitches giving the density increases have driven process evolution, incorporating changes such as the adoption of ArF photolithography, a switch to oxide interline dielectrics, high-aspect-ratio contacts, interpoly vias, and etched bit-lines.

Table 1 (see below) summarizes the reductions in interline spacing and coupling area, and changes in interline dielectric. However, it is noticeable that the vertical dimensions have not shrunk in parallel with the lateral features. In particular, the tunnel oxide has stayed in the 7–10nm range, and the ONO stack is consistently ~15nm, presumably because of the need to limit leakage currents.

It seems likely that the lithographic scaling of Flash memories will continue, but development in dielectric technology is necessary if vertical scaling is to proceed. Perhaps the introduction of strain engineering will provide an interim solution, as it has done in logic technology.

All in all, the evolution of NAND Flash provides a great example of the feedback loop between technology and products—the consumer products using high volumes of Flash would not be possible without the latest technology, but then the technology would not be evolving at the current hectic pace without the driving force of the product demand. Almost a type of perpetual motion!

Acknowledgments
I would like to thank Chipworks’ laboratory staff and process analysts, and our contractors, who actually did all the hard work of analyzing these complex devices. This article is based on a paper [7] given at the 2007 Advanced Semiconductor Manufacturing Conference in Stresa, Italy.

References
1. R. Arghavani et al., “Strain engineering in nonvolatile memories,” Semiconductor International, April 2006.
2. J.H. Park et al., “8Gb MLC (multi-level cell) NAND flash memory using 63nm process technology,” 2004 IEDM Technical Digest, pp. 873–876.
3. J.D. Lee, et al., “Effects of floating-gate interference on NAND flash memory cell operation,” IEEE Electron Device Letters, Vol. 23, No. 5, May 2002.
4. Chipworks calibrates measurements on its scanning electron microscopes, transmission electron microscope, and optical microscopes using measurement standards that are traceable to the International System of Units (SI). Fluctuations in the tool performance, coupled with variability in sample preparation and random errors, introduced during our analyses of the micrographs, yield an expanded uncertainty of +/-5%.
5. D-C. Kim et al., “A 2Gb NAND flash memory with 0.044µm2 cell size using 90nm Flash technology,” 2002 IEDM Technical Digest, pp. 873–876.
6. Y-S. Yim et al., “70nm NAND Flash technology with 0.025µm2 cell size for 4Gb Flash memory,” 2003 IEDM Technical Digest, pp. 819–822.
7. D. James, “Nano-scale Flash in the mid-decade,” Proceedings 2007 ASMC, Paper 12.4.

DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, djames@chipworks.com, www.chipworks.com.







































Table 1. The reductions in interline spacing and coupling area, and changes in interline dielectric
Part numberProcessFG width x heightFG interline coupling area (µm2)Interline spacing (nm)Interline dielectric
K9F2G08U0M, 2-Gb90nm SLC 150 × 80~0.012~83Nitride
K9G4G08U0M, 4-Gb90nm MLC150 × 56~0.008~72Mainly oxide
K9F4G08U0M, 4-Gb73nm SLC 90 × 86~0.008~60Nitride
K9G8G08U0M, 8-Gb60nm MLC 50 × 85~0.004~62Oxide

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