Samsung touts 30nm NAND flash using double-patterning

October 23, 2007 – Samsung Electronics Co. Ltd. says it has developed 64Gb multilevel cell NAND flash memory chip using 30nm process technology, built using double-patterning lithography, with commercial chips ready in about a year.

The new device utilizes a process called “self-aligned double patterning technology” (SaDPT), an upgrade from charge trap flash that Samsung has used for NAND flash on silicon nitride. in SaDPT, the first pattern transfer is a wider-spaced circuit design of the target process technology, then a second pattern transfer fills in the spaced area with a more closely designed pattern (see figure).

Samsung says it will use SaDPT with “existing photolithography equipment” for production using the 30nm process technology, targeting commercial production in 2009. In addition to the 64Gb MLC device, it has also built a 32Gb single-level cell NAND flash chip. Up to 16 64Gb flash devices can be combined into a 128GB memory card, capable of storing 80 DVD-quality-resolution movies, or 32k MP3 music files, the company said.

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