Double patterning will challenge litho, metrology, push feedback, computation

by Bob Haavind, Editorial Director, Solid State Technology

Feb. 26, 2008 – While 193nm immersion lithography has taken the industry to 45nm it will get progressively tougher to move below that. Lithographers will struggle with shrinking margins, more metrology and process control, along with extensive computation, plus double exposure for critical layers which multiplies their problems.

The SPIE Advanced Lithography Conference in San Jose, CA, is exploring this road ahead. Below 40nm, lithography becomes much more sensitive to stepper variation, and computational optimization will be required, according to Martin van den Brink, EVP, ASML, in a plenary talk. Lithography uniformity becomes critical, and metrology will be very difficult, especially with double exposure.

“Stepper controls are not well used today,” he said. It is possible to adjust dose point-by-point across the wafer, he suggested, but only with a tremendous amount of computation. Angle-resolved scatterometry feedback loops in production with a DoseMapper recipe might provide optimization. There also must be increased feedback from manufacturing to design, van den Brink added.

While EUVL continues on track for 22nm, he believes that memory makers will make strong use of double-patterning before going to EUV. Overlay and CD control using application-specific scanner tuning with fast, integrated metrology feedback will help make this possible, according to van den Brink. The process will also require pattern-split software.

D. Mark Duncan, president/CEO of Micron, agreed in his plenary talk that double patterning will be needed for future memory cells, but as the shrink continues, he foresees accelerating patterning costs. Going to 3D will forestall the move below 32nm for a time, he suggested.

Pushing NA higher for immersion lithography using new lens materials and a higher index-of-refraction fluid, could help reduce the challenge. But this will not be an option for 22nm, pointed out Toshikaya Umatata, GM of development headquarters for Nikon Precision, in a presentation a day earlier.

“High index does not match with the Roadmap,” he stated. Instead, at 22nm, EUVL will be the only candidate for general patterning, he added.

Micron’s Duncan did an analysis that supported this view. “I am confident that EUV is at the end of the Roadmap,” he stated. He sees EUV as the route to lowering rising patterning costs in the 2010-2012 timeframe. Duncan pointed out that chipmakers have to make massive bets on new factories, spending $3B on a new fab, much more than for an auto assembly plant, for example. Only an offshore rig, at $1.5-$2B, comes close. Yet, Duncan showed that the incremental gain in dollars/die would be shrinking significantly over the next few nodes.

ASML’s van den Brink took note of this investment concern in discussing the push toward higher productivity exposure tools. An analysis shows that acceleration is much more critical than scan speed, he explained. Right now, he said, an immersion tool can move at 600mm/sec, but to boost productivity further, the goal is to push that beyond 1m/sec, with lower defects and even tighter metrology overlay capability, moving from 4nm down to 2nm. Current 193nm immersion tools reach an NA of 1.35 without new lens materials and higher-index fluids, which is scalable down to 38nm, he said. Then double patterning, and eventually EUVL, will be needed.

While some experimental EUV tools are in operation, the technology will not be suited for volume production until an entire infrastructure is in place, pointed out Ben Eynon, associate director of SEMATECH’s lithography division in Albany, NY (assigned from Samsung). He reviewed the EUV infrastructure status at a pre-conference session organized by KLA-Tencor.

A major concern is an X-ray source that can deliver sufficient power to the wafer to meet reasonable throughput goals. Current sources can deliver 6W to an intermediate focus point, but 180W will be needed. “We need two orders of magnitude improvement, and that is a big challenge,” he said.

One source candidate is a discharge-produced plasma (DPP), but this involves a heavy heat load and does not scale well. More promising, according to Eynon, is a laser-produced plasma (LPP), using droplets of tin. The burst power needs to be focused, but the scalability is promising, he said.

EUVL will also require a resist that provides high resolution, allows adequate throughput, and minimizes line-edge roughness (LER). Right now, candidate resists that meet one requirement fail at the others, so improved materials will be needed to meet all three together.

Reflective reticles are essentially mirrors that must be flawless, Eynon explained. Any flaw on the glass substrate is greatly amplified after depositing 80 alternate layers of silicon and molybdenum over a 10hr period — any pit or particle would build up, making the reticle useless. Methods are being developed to remove any particles over 4nm high, and each layer may be smoothed out as deposition proceeds to minimize potential flaws. The eventual target is about 1 defect every 5 blanks or so, Eynon said.

For production, an EUV aerial imaging tool will be needed, he said, but the market will be so small that SEMATECH will need to help in the development.

“EUV still looks more cost-effective than double exposure, if we can develop it in a reasonable time,” Eynon explained. “That’s why we’re still pushing.” — B.H.

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