by M. David Levenson, Editor-in-Chief, Microlithography World
Feb. 28, 2008 – Getting the most function out of the least chip area has been the main goal of IC designers since the beginning of the industry. Their creativity gave rise to complex two-dimensional layouts that were shrunk geometrically one generation after another — until about the 90nm node. At that point, the fact that the circuit features had become so much smaller than the exposure wavelength made imaging problematic. Circuit variability increased and lithography hotspots appeared at corners, isolated contacts and other structures, limiting yield. Attempts to restrict designer creativity to manufacturable shapes through restrictive design rules had only limited success.
Now, Campbell, CA-based startup Tela Innovations proposes a radical step to solve the industry’s layout problems by employing only certain pre-defined linear topologies. Previous proposals to limit design flexibility in that way had been rejected because of the fear of increased circuit area and the cost of redesigning entire cell libraries. According to Neal Carney, Tela VP of marketing, those problems have now been overcome as the result of three years’ effort. The Tela Authoring System can convert the netlists of a 360 cell library to deterministic gridded design geometries in two weeks — with a 10%-15% reduction in chip area, according to Carney. Leakage and variability are also dramatically reduced for 45nm generation circuits.
Rather than restricting geometries, the Tela system is prescriptive: only certain things are allowed, but they are known to work. Thus the environment of every circuit element and cell is pre-defined by the “topology,” limiting context-dependent variation. The Tela process assigns one pitch and one orientation to all the lines forming the poly, metal1 and metal2 layers, avoiding “forbidden pitches” and other litho anomalies. Gaps in the lines define function. Since everything is placed on the grid, the vias are also on-grid, although not all grid sites are populated. Non-printing sub-resolution assist vias are placed at unused sites, facilitating the proper exposure of the desired contacts. Manufacturable implant geometries are also pre-defined.
Fig. 1 compares a block laid out in a conventional way with one having the same function laid out in Tela’s grating-like system. The simpler linear shapes are printed with greater fidelity, according to simulations provided by Brion Technologies.
Fig. 2 illustrates the reduction in gate length variation due to the increased regularity of the 1-D design. Since there are fewer short gates, leakage is reduced and circuit performance improved.
The circuit elements “snap” together (Fig. 3.), making layout and timing generation more efficient. Carney claimed that complex logic elements could be created in less than an hour.
The linear topologies also lend themselves to separation into two masks, or sequential lithography and deposition processes, for the double patterning technology needed for the 32nm node. Co-authors from Tela and Applied Materials presented one paper on how gridded design rules could be implemented with a self-aligned spacer double patterning process that used Applied APF (advanced patterning film) to fabricate geometries suitable for 22nm node Flash, SRAM and logic cells.
Tela was founded in 2005 by Scott Becker (CEO), Dhrumil Gandhi (COO) and John Malecki (chief architect), all of whom have background that include work with IP pioneer Artisan Components (now part of ARM). Michael Smayling, former CTO at Applied Materials and Fellow at Texas Instruments, is Tela’s SVP of product technology. The company completed its first round of financing in 2006 which enabled them to develop a proof of concept. Initial investors included Sand Hill Finance Company, Teton Capital, and Western Technology Investment. Later, Intel Capital and Asia Tech Investments added funds. Now it seeks to partner with library development teams and provide design services to the ASSP/ASIC industry. — M.D.L.