SEMATECH’s Arkalgud: A 3D/TSV route to higher IC densities

by Bob Haavind, Editorial Director, Solid State Technology

March 11, 2008 – Shrinking devices on an IC to increase density has been the industry’s primary means for following Moore’s Law for decades, but another route to higher density is going to 3D, pointed out Sitaram R. Arkalgud, director of SEMATECH’s 3D interconnect program. Already the industry is in Phase I of a trend toward 3D with packaging innovations, such as system-in-package (SiP) and package-on-package (PoP) approaches. But wire bonds on pads at the edges have been used for connections between chips. This requires long signal paths, slowing performance.

Much shorter signal paths could be provided by through-silicon vias (TSVs) that could be placed anywhere on each chip. This approach is already being used by Samsung with up to eight stacked die NAND flash or DRAM memory packages using TSVs — which is what Arkalgud called Phase II of the 3D transition. Instead of doing vias one at a time with a laser drill, they are done hundreds at a time using reactive-ion etching (RIE), and then copper plated. A big question about TSVs, according to Arkalgud, is the cost of the processing needed for etching the vias and plating through multi-layers of chips or wafers. Via widths might range from 1μm-50μm, with aspect ratios up to 10:1, which will be very hard to plate through. If copper-to-copper bonding is used, this can take several hours.

In Phase 3 of the 3D transition, there might be face-to-face bonding of chips which could make TSVs optional, Arkalgud explained, noting that Intel is taking this approach for an 80-core processor. If TSVs are used, they can be via-first, or backside via last approaches.

As TSV technology advances and becomes cost-effective (see figure 1), the industry can move to Phase 4 — multi-chip stacking and aggressive via pitch and diameter targets. Processes, including bonding and thinning, will become more “assembly-like,” he added. Cooling of the device stacks will be a problem, but a number of solutions are being explored, including using one layer as a cooling layer, adding microfluidic channels to carry off heat, or adding extra vias to enhance heat flow. Better modeling will be needed to determine the effectiveness of these various approaches.

One problem facing the industry, according to Arkalgud, is that many of these processes will overlap work done at a high-performance wafer fab and an assembly house, which might even be on different continents and operate with different cultures. Standards will be needed to allow convenient mix-and-match of various types of devices in either die-to-wafer or wafer-to-wafer stacks.

There are pros and cons to each of these approaches, Arkalgud explained (see figure 2). For wafer-to-wafer stacking to work, all die will have to be the same size and very high yield will be required to make sure all the die in a stack are good. If the chipmaker wants a heterogeneous stack, with flash, SRAM, DRAM, and microprocessors plus other devices, die sizes will be different and even wafer sizes may vary. This mix-and-match approach can be done with die-to-wafer stacking. He pointed out that while cost will be a deciding factor on whether the TSV approach is used, it rates as excellent for all other critical factors, such as performance, power, functionality, and time-to-market. The SiP approach would have lower performance, and the 2D, SoC approach would take a much longer time-to-market, for example.

The 3D approach also might be an enabler for combining other technologies with ICs, such as optoelectronics, MEMS, biosensors, and others.

Despite the benefits of 3D, Arkalgud explained that 3D technology can only advance through a wide collaborative effort across many parts of the industry. There are many different possible integration approaches and bonding methods, and there is no benchmarking methodology for comparing tool performance, for example. Also, there are gaps in design and testing methodologies. Many options must be narrowed to a few most attractive approaches for critical mass to develop and a necessary infrastructure to develop.

SEMATECH sees the need for a 3D roadmap, and is working with the International Technology Roadmap for Semiconductors to develop specifications for when certain levels of precision will have to be reached. — B.H.

Click here for more presentations from the SEMI breakfast: Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology. And Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

NEW PRODUCTS

KLA-Tencor announces new defect inspection systems
07/12/2018KLA-Tencor Corporation announced two new defect inspection products at SEMICON West this week, addressing two key challenges in tool and process monit...
3D-Micromac unveils laser-based high-volume sample preparation solution for semiconductor failure analysis
07/09/2018microPREP 2.0 provides order of magnitude time and cost savings compared to traditional sample...
Leak check semiconductor process chambers quickly and reliably
02/08/2018INFICON,a manufacturer of leak test equipment, introduced the UL3000 Fab leak detector for semiconductor manufacturing maintenance teams t...