Intel: EUV seen ready at 16nm; mask infrastructure challenges are key

by Debra Vogler, Senior Technical Editor, Solid State Technology

Intel’s recent disclosure that EUV would not be ready in time to insert into the company’s 22nm manufacturing ramp-up (with high-volume production planned for 2011) probably was not surprising to close followers of NGL technology. Intel’s own lithography roadmap (see Fig. 1) shows immersion lithography living on by way of various extensions, which could include higher NAs, double-patterning, or split-patterning, according to ConFab presenter, Janice Golda, director, lithography capital equipment development at Intel. The company has stated that it will begin manufacturing at 32nm in 2009.

Golda told SST that the company plans for 16nm node high-volume production sometime around 2013, and that while a technology decision isn’t needed today, “when mature enough, [EUV] is expected to be the compelling choice.” She added that EUV would likely be extended using techniques similar to those used for extending immersion lithography.

Figure 1. Intel critical litho roadmap. (Source: Intel)

Commenting on the status of high-index immersion lithography, Golda noted that there’s been some reasonable progress in high-index materials for lens systems, but the problem is getting enough material for the scale-up. Also a problem is that there are no existing Gen 3 fluids to enable very high-NA. “So it comes down to economics for the scanner manufacturers,” she said. “If you have something with limited extendibility and a non-trivial development project, is it worth your resources to go after it?” A key consideration, she noted, is whether or not the market window shrinks, eliminating the opportunity.

Having multiple industry options for NGL requires a healthy mask infrastructure, Golda pointed out (see Fig. 2). “We need solutions for mask industry economics,” she said. “There are challenges with the volume of data needed for very low k1 lithography and EUV mask tools. We would like to see industry collaboration because of these mask infrastructure economic challenges.”

Figure 2. Mask infrastructure health is critical. (Source: Intel)

Key challenges in mask infrastructure, Golda noted, include: development of advanced mask writers, as these help enable all lithography approaches under consideration; and development of advanced EUV mask inspection tools –particularly ones to detect tiny particles on mask blanks, and determine if defects on patterned masks will print in the wafer fab. “We believe that new alliances and new collaboration models can help deliver these capabilities to the market,” she said. “In addition to working with the ‘usual suspect’ consortia, we see opportunities for supplier-supplier collaboration to mate novel technologies with established platform capabilities, as well as for enhanced supplier-customer collaboration,” she said, perhaps using models such as ‘ad hoc’ alliances in which suppliers and customers with similar needs work together. — D.V.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

NEW PRODUCTS

KLA-Tencor announces new defect inspection systems
07/12/2018KLA-Tencor Corporation announced two new defect inspection products at SEMICON West this week, addressing two key challenges in tool and process monit...
3D-Micromac unveils laser-based high-volume sample preparation solution for semiconductor failure analysis
07/09/2018microPREP 2.0 provides order of magnitude time and cost savings compared to traditional sample...
Leak check semiconductor process chambers quickly and reliably
02/08/2018INFICON,a manufacturer of leak test equipment, introduced the UL3000 Fab leak detector for semiconductor manufacturing maintenance teams t...