by Dick James, senior technology adviser, Chipworks
Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.
Dec. 18. 2008 – The morning was an endurance test, with nine consecutive papers on 22, 32, and 45nm devices. A lot of strained silicon, and not a few strained attendees! So it’s a bit tedious, but rather than cherry-pick, let’s run through the list from Session 27:
The IBM Alliance kicked off the day again with the 0.1 μm2 SRAM cell that was announced back in the fall, fabbed at the Albany Nanofab. With a 90nm contacted gate pitch and gate length of 25nm, a suite of different techniques were used to create the test chips.
Not least the wet lithography; the active SOI areas were patterned using crossed quadrupole illumination; the gates used double exposure, double etch (DEDE, or DE2, or LELE — acronyms are taking over again) with dipole illumination; the contacts used DE2 with a tri-layer resist; and M1 was patterned with double masking using dipole illumination and a single etch.
Other process elements are 45nm thin SOI, dual high-k metal gates (HK+MG), co-implants at the SDE/halo, and copper contacts with Ru liners. As this was a proof-of-concept exercise, stress techniques were not used, although in answer to a question the presenter implied that they were being introduced.
Next up was TSMC with a 32nm gate-first HK+MG process, with a 9Å EOT, 30nm Lg and 130nm contacted gate pitch, with an SRAM cell size of 0.15 μm2. The usual suite of stress tools was used, SMT, e-SiGe, and dual stress liners (DSL), and junction profiles were optimized with co-implants. The BEOL has ten layers of copper, and 2nd generation low-k dielectric (k~2.55) at the lower levels (Black Diamond 2?).
IBM were back up again, this time the Common Platform et al, with a 32nm, single gate-first HK+MG bulk technology with 126nm contacted gate pitch and 0.157 μm2 SRAM cell. The usual stress trio of SMT+DSL+e-SiGe is present, and thin-barrier copper with ELK (extreme low-k, k~2.4) in the BEOL.
Intel’s turn this time, with tweaks to their 45nm process to add low-power and RF/mixed signal elements to the designer toolbox. After running through the base process, we had a shopping list of new features. Some were obvious — the super-thick 8μm redistribution layer is ideal for inductors, for example — but others need new process modules.
High voltage I/O transistors with a thicker SiO2 layer have been added, as have low-power transistors with slightly longer gate lengths and tuned S/Ds to reduce junction leakage (co-implants?). Add in capacitors, varactors, one-time programmable fuses, and RF transistors and you have quite a shopping bag. At the end of the paper someone asked if there were poly devices (the replacement gate has not been replaced), which was met by the usual stony “I can’t answer that” response — which makes us all think that it’s at least being looked. I must admit that at Chipworks we have thought about that possibility, at least for fuses.
Figure 1: TEMs of nMOS and pMOS logic (left top/bottom) and I/O transistors (right top/bottom). Note the thicker oxide layer in I/O devices. (Source: Intel)
Now the NEC/Toshiba consortium; a 40nm high-k dielectric (but not metal gate) technology, with 40nm gate length, 168nm contacted gate pitch, 0.195μm2 SRAM cell, and a thicker EOT of 1.75nm. A couple of years ago NEC announced a 55nm process with a hafnium-based gate dielectric, and it looks like this is a shrink.
They went into quite a lot of detail about the source/drain engineering, reducing junction leakage by using a Ge + N pre-amorphization implant before the SDE and halo implants, and putting a lot of work into the activation anneal sequence to co-optimize it with the SMT stress application (nitride stress is also used, no mention of DSL).
The gate litho is single exposure to keep costs down, and the BEOL has the choice of low-k dielectric, k~2.75 or 2.55, depending on cost requirement (Black Diamond 1 or 2?). This paper is worth going through in detail, as it discusses stuff usually described with a phrase or two.
Figure 2: 40nm transistors with HfO dielectric. Note the lack of thick dark metal layer. (Source: NEC/Toshiba)
I took a pass on these — I needed a break!
Now we’re into the late news papers — NEC/Toshiba again, but 32nm this time, again with a cost conscious emphasis — the target was to reduce per-function cost by 50% from the 45nm node. They claimed that this was achieved with a standard cell gate density of 3650K gates/mm2; it sounds impressive!
They achieve this by using single-pass lithography and gate-first HK+MG transistors. Contacted gate pitch is 120nm, and SRAM cell size is 0.124μm2, but no other details were available. By the litho images below, it looks like the full suite of OPC and dipole/quadrupole illumination tricks is being used.
Figure 3: [Top] 0.124 μm2 SRAM cell, (A) gates, (B) contacts, (C) Metal 1. [Bottom] D-type flip-flop, (left) active area, gates, and contacts, (right) Metal 1. (Source: NEC/Toshiba)
This was the Intel 32nm paper that got the pre-publicity back in the fall. EOT is down a smidge to 9Å, gate length is 30nm, SRAM cell 0.171μm2, we have 4th-generation strain, and the BEOL is 9 metal levels with slight tweaks to the low-k package, but still low-k/SiCN.
It struck me when we took apart the 45nm part that the technology had legs, and was scalable to 32nm; I think what we’re seeing here is essentially a shrink (except, of course, with wet litho); we’ll find out at the backend of next year when the chips appear on the market.
So as you can see the morning session was very intense, and there were other papers in other sessions that I wanted to get to. In the afternoon session 37 was more focused on source/drain engineering, so I wound down by sitting on a couple of those.
Samsung has been trying out different co-implants and anneal cycles on their 45nm base process. Ge is used as a pre-amorphization implant before both n- and pMOS SDE and halo implants, and this was modified to Ge + C or F, and cluster carbon (C16H10) was tried to replace both.
In nMOS the cluster-C seems to give the best results, sharpening up the halo profile, and reducing junction leakage. PMOS it was not quite so positive, since the halo profile was sharpest with the Ge + F combination; but overall the clusters seemed to do best. Boron clusters were also tried in pMOS, but that led to an increase in Vt variation.
37.4Toshiba did an interesting analysis by atom probe of platinum doping in nickel silicide. This is an ongoing trend that we have seen in our analyses, almost the majority of 65nm parts have Pt-doped silicides (Intel is an exception); it is claimed to reduce contact resistance. Atom probe is a relatively new technique, but it has much better resolution than SIMS, since it counts individual atoms (check www.Imago.com).
The analyses showed that the platinum segregated both at the surface and the silicide interface in the source/drains, which actually jives with an atom probe analysis we did of a UMC-fabbed Xilinx part; we saw the same feature in the gate polysilicon. And it did help contact resistance.
Phew! That’s it for IEDM ’08. Maybe I’ll see you next year… If the industry’s still around. — D.J.
DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, email@example.com, www.chipworks.com.