By Yann Guillou, ST-Ericsson Wireless and Eric Saugier, STMicroelectronics
3D Integration, through silicon via (TSV), 3D packaging, 3D TSV, 3D system-in-package (SiP), 3D system-on-chip (SoC), and 3D system-on-package (SoP) are some of the hottest topics presented at conferences to standing-room only audiences or read about in popular tech magazines. All of these are definitively trendy terms; no one would argue to the contrary. So it’s about time to take a serious look at 3D in its broadest meaning.
Terminology is a real mess; everyone uses their own terms and often mixes them all together. The confusion mainly stems from partial understanding. We hope we can bring a bit of clarity to the chaos.
First of all, 3D configurations are not new at all. 3D configurations at the packaging level have been around for years.
Stacked dies with wire bonds in BGA are an example of this. For instance, in 2003, STMicroelectronics announced a stack of 10 dice, a world record at that time. Since then, some packaging houses and IDMs have produced stacks with up to 40 dice! No one would argue that 40 dice on the vertical axis is not 3D.
Other 3D packaging configurations are called package-on-package (PoP), or package-in-package (PiP) and other nomad devices. Some packaging evolutions of PoP and PiP still using the third dimension have been lately announced by top SATS providers (Fan-In PoP, MaPPoP, through-mold-via TMV