AMAT Joins EMC-3D Consortium

Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium. Applied offers process and integration capabilities in the fields of etching, dielectric and metal deposition, chemical-mechanical polishing, metrology, and inspection. These capabilities will be used for developing a cost-effective and manufacturable for 3D chip stacking and MEMS integration.

Through-silicon via technology is a new method of combining integrated circuits in a vertical stack to enable higher functionality and lower power consumption in a small footprint. While employing many standard chip processes, TSVs present several new technical challenges for production-worthy manufacturing: maintaining wafer structural and edge integrity of thin wafers, stress and thermal profile control, via processing and device reliability.

“Applied Materials sees the TSV approach as an important enabling technology for tomorrow’s sophisticated image sensors, memory and mixed-signal applications,” said Hans Stork, group vice president and CTO of Applied’s Silicon Systems Group. “Joining forces with other leading equipment and materials suppliers is an effective way to qualify contiguous processes, drive down the cost and enable the widespread adoption of TSV technology. By deploying fabrication equipment, materials and process technology from the EMC-3D member companies, our customers can take advantage of a complete, validated process flow, greatly reducing their own development time and initial investment.”

“We’re very pleased to bring Applied Materials into this consortium and look forward to a productive relationship in developing cost-effective TSV solutions for chip stacking applications,” said Paul Siblerud, EMC-3D chairman and vice president of marketing at Semitool. “EMC-3D is currently at the mid-point of a 3 year objective to bring cost-effective TSV to market. Each member is addressing the technical integration challenges of TSV technology for chip stacking and advanced MEMS/sensors packaging.”

The original goal of the consortium was to create a robust integrated process flow at a cost of less than $200USD per wafer. That goal has expanded to include both a via-first (iTSV™) and via-last (pTSV™) process flow at a total cost of ownership of under $150USD.

Silberud added “There are few bright spots in the semiconductor market currently, however, chip stacking TSV has both technical and cost advantages and are still finding research and development investment and priority. The consortium is actively working on 300mm integration of a Cu-TSV suitable for both iTSV and pTSV (via-first interconnect and via-last packaging). Currently the members are showing a $189/wafer total CoO with a clear roadmap to sub-$150/wafer CoO.”

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